-
公开(公告)号：US09335972B2
公开(公告)日：2016-05-10
申请号：US14093040
申请日：2013-11-29
申请人： Kaiyuan Yang , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick , Michael B. Henry , Yoonmyung Lee
发明人： Kaiyuan Yang , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick , Michael B. Henry , Yoonmyung Lee
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.
摘要翻译： 真正的随机数发生器包括环形振荡器，其在振荡开始时刻被触发以在第一振荡模式下开始振荡。 第一种振荡模式最终会依赖于热噪声而崩溃到第二种振荡模式。 测量从振荡开始时间到振荡器塌陷到第二模式的时间的崩溃时间，并且这可以用于确定随机数。 TRNG可以使用标准数字技术完全合成，能够提供高随机性，良好的吞吐量和能量效率。
-
公开(公告)号：US20150154006A1
公开(公告)日：2015-06-04
申请号：US14093040
申请日：2013-11-29
申请人： Kaiyuan YANG , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick , Michael B. Henry , Yoonmyung Lee
发明人： Kaiyuan YANG , Dennis Michael Sylvester , David Theodore Blaauw , David Alan Fick , Michael B. Henry , Yoonmyung Lee
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.
摘要翻译： 真正的随机数发生器包括环形振荡器，其在振荡开始时刻被触发以在第一振荡模式下开始振荡。 第一种振荡模式最终会依赖于热噪声而崩溃到第二种振荡模式。 测量从振荡开始时间到振荡器塌陷到第二模式的时间的崩溃时间，并且这可以用于确定随机数。 TRNG可以使用标准数字技术完全合成，能够提供高随机性，良好的吞吐量和能量效率。
-
公开(公告)号：US20100217562A1
公开(公告)日：2010-08-26
申请号：US12379617
申请日：2009-02-25
申请人： David Theodore Blaauw , Dennis Michael Sylvester , David Alan Fick , Stuart David Biles , Michael John Wieckowski , Scott McLean Hanson , Gregory Kengho Chen
发明人： David Theodore Blaauw , Dennis Michael Sylvester , David Alan Fick , Stuart David Biles , Michael John Wieckowski , Scott McLean Hanson , Gregory Kengho Chen
CPC分类号： G05B21/02 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.
摘要翻译： 一种用于处理数据2的装置设置有时间 - 数字转换器18，其用于通过一个或多个通过处理级的信号路径来测量信号处理延迟。 该测量的延迟产生表示已经测量的信号处理延迟的多个实例的延迟值。 在软件控制下执行分析以基于已经产生的延迟值来估计通过处理阶段的最差情况信号处理延迟。 进行装置的工作参数（例如电源电压和时钟频率）的调整，以通过处理阶段提供足够的时间余量，以满足在没有过多余量的情况下估计的最差情况信号处理延迟。
-
公开(公告)号：US20150015305A1
公开(公告)日：2015-01-15
申请号：US13940864
申请日：2013-07-12
申请人： Bharan GIRIDHAR , Matthew Rudolph Fojtik , David Alan Fick , Dennis Michael Sylvester , David Theodore Blaauw
发明人： Bharan GIRIDHAR , Matthew Rudolph Fojtik , David Alan Fick , Dennis Michael Sylvester , David Theodore Blaauw
IPC分类号： H03K19/003
CPC分类号： H03K3/0375 , H03K5/133 , H03K5/135
摘要： Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.
摘要翻译： 同步电路2包括产生由脉冲放大电路8脉冲放大以产生脉冲放大信号的第一级状态信号的第一动态电路级4。 脉冲放大信号被提供给第二动态电路级6，其中它用于控制第二级状态信号的产生。 脉冲放大电路8包括串联连接的偏斜反相器20,22。脉冲放大电路8的作用是降低第二动态级6的输出中的亚稳态概率。
-
公开(公告)号：US20110202786A1
公开(公告)日：2011-08-18
申请号：US12656708
申请日：2010-02-12
IPC分类号： G06F1/12
CPC分类号： G06F11/0793 , G06F9/3869 , G06F11/0721
摘要： A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data, the plurality of synchronisation circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronisation circuits is stable during a predetermined time and for signalling an error if the data input is not stable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronisation circuits that contains a subsequent synchronisation circuit that said synchronisation circuit with said unstable input is configured to transmit said data to; each of said group of synchronisation circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronisation circuits that said group of synchronisation circuits is configured to transmit data to or receive data from; each of said group of synchronisation circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronisation circuits.
摘要翻译： 公开了一种用于处理数据的数据处理电路。 数据处理电路包括：多个同步电路，用于响应于时钟信号捕获和发送数据;以及多个组合电路，布置在用于处理数据的同步电路之间，多个同步电路被布置在至少两个 团体 一个误差检测电路，用于确定输入到多个同步电路之一的数据在预定时间内是否稳定，以及如果数据输入不稳定则用于发信号通知，该预定时间小于时钟信号的半个周期 ; 响应于所述错误检测电路的控制电路发信号通知所述错误，以将控制信号发送到所述同步电路组中的至少一个，该同步电路组包含随后的同步电路，所述同步电路与所述不稳定输入被配置为传送所述数据; 所述同步电路组中的每一个被配置为响应所述控制信号的接收以停止一个时钟周期，并且将失速信号发送到至少一组另一组同步电路，所述同步电路组被配置为将数据传输到 或接收数据; 所述组同步电路中的每一个被配置为响应于所述失速信号的接收，只要它们在前一时钟周期内没有停止以停止时钟周期，并且将失速信号发送到所述至少另一组同步电路。
-
公开(公告)号：US08407025B2
公开(公告)日：2013-03-26
申请号：US12379617
申请日：2009-02-25
申请人： David Theodore Blaauw , Dennis Michael Sylvester , David Alan Fick , Stuart David Biles , Michael John Wieckowski , Scott McLean Hanson , Gregory Kengho Chen
发明人： David Theodore Blaauw , Dennis Michael Sylvester , David Alan Fick , Stuart David Biles , Michael John Wieckowski , Scott McLean Hanson , Gregory Kengho Chen
CPC分类号： G05B21/02 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.
摘要翻译： 一种用于处理数据2的装置设置有时间 - 数字转换器18，其用于通过一个或多个通过处理级的信号路径来测量信号处理延迟。 该测量的延迟产生表示已经测量的信号处理延迟的多个实例的延迟值。 在软件控制下执行分析以基于已经产生的延迟值来估计通过处理阶段的最差情况信号处理延迟。 进行装置的工作参数（例如电源电压和时钟频率）的调整，以通过处理阶段提供足够的时间余量，以满足在没有过多余量的情况下估计的最差情况信号处理延迟。
-
公开(公告)号：US08276014B2
公开(公告)日：2012-09-25
申请号：US12656708
申请日：2010-02-12
IPC分类号： G06F1/12
CPC分类号： G06F11/0793 , G06F9/3869 , G06F11/0721
摘要： A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronization circuits for processing the data, the plurality of synchronization circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronization circuits is stable during a predetermined time and for signalling an error if the data input is unstable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronization circuits that contains a subsequent synchronization circuit that said synchronization circuit with said unstable input is configured to transmit said data to; each of said group of synchronization circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronization circuits that said group of synchronization circuits is configured to transmit data to or receive data from; each of said group of synchronization circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronization circuits.
摘要翻译： 公开了一种用于处理数据的数据处理电路。 数据处理电路包括：多个同步电路，用于响应于时钟信号捕获和发送数据;以及多个组合电路，布置在用于处理数据的同步电路之间，多个同步电路被布置在至少两个 团体 一个误差检测电路，用于确定输入到多个同步电路之一的数据在预定时间内是否稳定，如果数据输入不稳定则用于发信号通知，该预定时间小于该时钟信号的一半周期; 响应于所述错误检测电路的控制电路发信号通知所述错误，以将控制信号发送到所述同步电路组中的至少一个，该同步电路组包含随后的同步电路，所述同步电路与所述不稳定输入被配置为传送所述数据; 所述同步电路组中的每一个被配置为响应所述控制信号的接收以停止一个时钟周期，并且将失速信号发送到至少一组另一组同步电路，所述同步电路组被配置为将数据传输到 或接收数据; 所述组同步电路中的每一个被配置为响应于所述失速信号的接收，只要它们在前一时钟周期内没有停止以停止时钟周期，并且将失速信号发送到所述至少另一组同步电路。
-
公开(公告)号：US07864562B2
公开(公告)日：2011-01-04
申请号：US12379820
申请日：2009-03-02
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： A memory cell 36 within an integrated circuit memory is provided with an access controller 32 coupled to a first pass gate 38 and a second pass gate 40. During a write access to the memory cell 38 both the first pass gate 38 and the second pass gate 40 are opened. During a read access, the first pass gate 38 is opened and the second pass gate 40 is closed. This asymmetry in the read and write operations permits an asymmetry in the gates forming the memory cell 36 thereby permitting changes to increase both read robustness and write robustness. The asymmetry in the design parameters of different gates can take the form of varying the gate length, the gate width and the threshold voltage so as to vary the conductance of different gates to suit their individual role within the memory cell 36 which is operating in the asymmetric manner provided by the separate word line signals driving read operations and write operations.
摘要翻译： 集成电路存储器内的存储单元36具有耦合到第一传输门38和第二传输门40的访问控制器32.在对存储单元38的写访问期间，第一传输门38和第二传输门 40打开。 在读取访问期间，打开第一传递门38并关闭第二传递门40。 读写操作中的这种不对称允许形成存储单元36的门的不对称性，从而允许改变增加读稳健性和写鲁棒性。 不同栅极的设计参数中的不对称可以采取改变栅极长度，栅极宽度和阈值电压的形式，以便改变不同栅极的电导以适应其在存储单元36内的各自的作用 由分离的字线提供的非对称方式驱动读操作和写操作。
-
公开(公告)号：US08230152B2
公开(公告)日：2012-07-24
申请号：US12458511
申请日：2009-07-14
IPC分类号： G06F13/00
CPC分类号： G11C7/10
摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection.
摘要翻译： 交叉开关电路以及这种交叉电路的操作方法。 交叉开关电路具有数据输入路径和数据输出路径的阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交点处，提供交叉开关单元，其包括可编程以存储路由值的配置存储电路，传输电路和仲裁电路。 在传输操作模式中，传输电路响应于路由值是第一值，指示数据输入路径应耦合到数据输出路径，以检测沿数据输入路径输入的数据，并输出 在相关联的交叉路口上的数据输出路径上的该数据的指示。
-
10.发明申请Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry 有权用于应用自适应优先权方案的交叉开关电路和这种交叉电路的操作方法公开(公告)号：US20110138098A1
公开(公告)日：2011-06-09
申请号：US12926462
申请日：2010-11-18
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , H03K17/693
摘要： Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.
摘要翻译： 交叉开关电路具有数据输入和输出路径阵列，其中数据输出路径横向于数据输入路径。 在数据输入路径和数据输出路径之间的每个交点处，提供交叉开关单元，其包括可编程以存储路由值的配置存储电路，发送电路和仲裁电路。 在传输操作模式中，传输电路响应于路由值是第一值，指示数据输入路径应耦合到数据输出路径，以检测沿数据输入路径输入的数据，并输出 在相关联的交叉路口上的数据输出路径上的该数据的指示。 在仲裁操作模式中，仲裁电路可操作以选择性地修改所述多个位线上的电压，以便应用自适应优先级方案。
-
-
-
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.054 秒)
