公开(公告)号：US20230187502A1

公开(公告)日：2023-06-15

申请号：US17983375

申请日：2022-11-08

Applicant: Adamantite Technologies LLC

Inventor： Eric David Bauswell

IPC: H01L29/16 ,  H01L21/02 ,  C23C14/04 ,  C23C14/06 ,  H01L29/167 ,  H01L29/66 ,  H01L21/82 ,  C23C14/28 ,  B82Y10/00 ,  B82Y40/00

CPC classification number: H01L29/1602 ,  H01L21/02527 ,  H01L21/02115 ,  C23C14/048 ,  C23C14/0611 ,  H01L29/167 ,  H01L21/02266 ,  H01L29/66045 ,  H01L29/66977 ,  H01L21/0257 ,  H01L21/02631 ,  H01L21/8206 ,  C23C14/28 ,  H01L21/02678 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02576 ,  H01L28/22 ,  H01L21/02581 ,  H01L28/40 ,  H01L29/66015 ,  C23C14/221

Abstract: A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

公开(公告)号：US09012293B2

公开(公告)日：2015-04-21

申请号：US13738604

申请日：2013-01-10

Applicant: GLOBALFOUNDARIES Singapore Pte. Ltd.

Inventor： Chang Yong Xiao ,  Roderick Miller ,  Jie Chen

IPC: H01L21/20 ,  H01L21/76 ,  H01L27/11 ,  H01L29/00 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/22 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL.

Abstract translation: 提供了一种用于在MOL工艺中形成夹层镶嵌电阻器的方法以及所得到的器件。 实施例包括在基板上形成包括层间电介质（ILD），第一电介质层和牺牲层（SL）的膜堆叠; 去除所述SL和所述第一介电层的一部分，形成第一空腔; 在第一腔中和SL上保形地形成电阻材料层; 在所述电阻材料层上沉积第二电介质层并填充所述第一腔; 以及去除所述第二电介质层，所述电阻材料层不在所述第一腔中，以及所述SL的至少部分深度。

公开(公告)号：US20140291701A1

公开(公告)日：2014-10-02

申请号：US14353990

申请日：2012-03-05

Applicant: Yukimasa Hayashida

Inventor： Yukimasa Hayashida

IPC: H01L49/02 ,  H01L29/16 ,  H01L23/498

CPC classification number: H01L28/22 ,  H01L23/49838 ,  H01L25/16 ,  H01L29/1608 ,  H01L2924/0002 ,  H01L2924/10272 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09045 ,  H05K2201/09745 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device that allows the life of solder joint parts of electronic components to be increased. The semiconductor device according to the present invention includes ceramic, an upper pattern formed on the ceramic, and a resistor connected onto the upper pattern via solder. The upper pattern has a portion formed in a recess shape, the portion being connected to the resistor via the solder.

Abstract translation: 本发明的一个目的是提供一种能够增加电子部件的焊接部件的寿命的半导体装置。 根据本发明的半导体器件包括陶瓷，形成在陶瓷上的上部图案，以及通过焊料连接到上部图案上的电阻器。 上部图案具有形成为凹部形状的部分，该部分通过焊料连接到电阻器。

公开(公告)号：US08101529B2

公开(公告)日：2012-01-24

申请号：US12526245

申请日：2008-01-18

Applicant: Kaoru Narita

Inventor： Kaoru Narita

IPC: H01L21/82

CPC classification number: H01L27/0629 ,  B82Y10/00 ,  G11C13/025 ,  G11C17/16 ,  G11C17/165 ,  H01C7/006 ,  H01C17/0652 ,  H01L28/22 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/961

Abstract: A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a first electrode and a second electrode, wherein the first concentration is 1(E10−4 g/ml or higher and the second concentration lower than 1(E10−5 g/ml.

Abstract translation: 一种能够提供高度可靠的电阻或熔丝的碳纳米管电阻器的制造方法。 该方法包括将挥发性溶剂中的碳纳米管引入第一浓度并进行超声波处理从而获得初始溶液的步骤; 稀释步骤，在超声波处理下用挥发性溶剂逐步稀释初始溶液，以将其调节至第二浓度，从而获得涂布溶液; 以及在第一电极和第二电极之间施加涂布溶液的步骤，其中第一浓度为1（E10-4g / ml或更高，第二浓度低于1（E10-5g / ml）。

公开(公告)号：US20230317770A1

公开(公告)日：2023-10-05

申请号：US17885570

申请日：2022-08-11

Applicant: Taiyuan University of Technology ,  Institute of New Materials and Chemical Engineering, Zhejiang University, Shanxi

Inventor： Yuying XI ,  Yanxia CUI ,  Kun HU ,  Yuan TIAN ,  Guohui LI ,  Bingshe XU

IPC: H01L49/02

CPC classification number: H01L28/22 ,  H01L21/02052

Abstract: Disclosed is a high-resistance resistor based on silicon carbide. The resistor includes a semi-insulating 4H-SiC silicon carbide substrate, a silicon surface and a carbon surface of the silicon carbide substrate are provided with symmetrical atomic-thickness aluminum oxide insulating layers, thicknesses of the aluminum oxide insulating layers are 0.2 nm-2 nm, conductive metal electrodes are formed at two sides of the aluminum oxide insulating layers through evaporation, and thicknesses of the metal electrodes are 100 nm-500 nm. The present disclosure uses a high-resistance resistor based on silicon carbide that has the above structure, makes an ohmic contact electrode on a semi-insulating silicon carbide substrate, thus obtaining a resistor with a resistance of 100 TΩ or more, and satisfying requirements of the precision measurement industry.

公开(公告)号：US20180006121A1

公开(公告)日：2018-01-04

申请号：US15627426

申请日：2017-06-19

Applicant: Adamantite Technologies LLC

Inventor： Eric David Bauswell

IPC: H01L29/16 ,  H01L49/02 ,  C23C14/06 ,  C23C14/22 ,  H01L21/02 ,  H01L27/06 ,  H01L29/167

CPC classification number: H01L29/1602 ,  C23C14/048 ,  C23C14/0611 ,  C23C14/22 ,  H01L21/02527 ,  H01L21/0257 ,  H01L21/02631 ,  H01L21/8206 ,  H01L27/06 ,  H01L27/092 ,  H01L28/22 ,  H01L29/167 ,  H01L29/66045

Abstract: A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

公开(公告)号：US09252142B2

公开(公告)日：2016-02-02

申请号：US14141530

申请日：2013-12-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ming Zhu ,  Yiang Aun Nga

IPC: H01L29/66 ,  H01L27/06 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/28123 ,  H01L28/22 ,  H01L28/24 ,  H01L29/66545

Abstract: Integrated circuits with a resistance element and gate-last techniques for forming the integrated circuits are provided. An exemplary technique includes providing a semiconductor substrate that includes a shallow trench isolation (STI) structure disposed therein. A dummy gate electrode structure is patterned overlying semiconductor material of the semiconductor substrate, and a resistor structure is patterned overlying the STI structure. The dummy gate electrode structure and the resistor structure include a dummy layer overlying a metal capping layer. A gate dielectric layer underlies the metal capping layer. An interlayer dielectric layer is formed overlying the semiconductor substrate and the STI structure. End terminal recesses for the resistance element are concurrently patterned through the dummy layer of the resistor structure along with removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess. Metal gate material is deposited in the end terminal recesses and a gate electrode recess.

Abstract translation: 提供了具有用于形成集成电路的电阻元件和栅极最后技术的集成电路。 一种示例性技术包括提供包括设置在其中的浅沟槽隔离（STI）结构的半导体衬底。 虚拟栅电极结构被图案化在半导体衬底的半导体材料上，并且将电阻器结构图案覆盖STI结构。 虚拟栅电极结构和电阻结构包括覆盖金属覆盖层的虚设层。 栅极电介质层位于金属覆盖层的下面。 层叠电介质层形成在半导体衬底和STI结构之上。 用于电阻元件的端部端子凹槽同时通过电阻器结构的虚设层图案化，同时去除虚拟栅电极结构的虚设层以形成栅电极凹槽。 金属栅极材料沉积在端子端子凹槽和栅电极凹槽中。

公开(公告)号：US20150171158A1

公开(公告)日：2015-06-18

申请号：US14569975

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Greg Charles BALDWIN ,  Kamel BENAISSA ,  Sarah LIU ,  Song Zhao

IPC: H01L49/02 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L28/22 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/0629 ,  H02J7/0044 ,  H02J7/025

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract translation: 一种将低TCR电阻添加到基准CMOS制造流程的方法。 在CMOS制造流程中形成低TCR电阻器的方法。 在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。

公开(公告)号：US20140225066A1

公开(公告)日：2014-08-14

申请号：US14124274

申请日：2012-06-18

Applicant: Heiko B. Weber ,  Michael Krieger ,  Stefan Hertel ,  Florian Krach ,  Johannes Jobst ,  Daniel Waldmann

Inventor： Heiko B. Weber ,  Michael Krieger ,  Stefan Hertel ,  Florian Krach ,  Johannes Jobst ,  Daniel Waldmann

IPC: H01L29/16 ,  H01L49/02

CPC classification number: H01L29/1606 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/8213 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/22 ,  H01L28/40 ,  H01L29/1608 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/812 ,  H01L29/872

Abstract: An electronic device (1) includes a semiconductor substrate (3) having a front surface (7), a first electrode (8) and a second electrode (9) disposed on the front surface (7) of the substrate (3), wherein the first electrode (8) and the second electrode (9) each have at least one epitaxial graphene monolayer (10). The at least one epitaxial graphene monolayer (10) of the first electrode (8) forms an ohmic contact with the substrate (3) and the at least one epitaxial graphene monolayer (10) of the second electrode (9) forms a Schottky barrier with the substrate (3).

Abstract translation: 电子设备（1）包括具有前表面（7），设置在基板（3）的前表面（7）上）的第一电极（8）和第二电极（9）的半导体基板（3），其中 第一电极（8）和第二电极（9）各自具有至少一个外延石墨烯单层（10）。 第一电极（8）的至少一个外延石墨烯单层（10）与衬底（3）形成欧姆接触，并且第二电极（9）的至少一个外延石墨烯单层（10）形成肖特基势垒，具有 基板（3）。

公开(公告)号：US20130049159A1

公开(公告)日：2013-02-28

申请号：US13222048

申请日：2011-08-31

Applicant: Gerhard Schmidt

Inventor： Gerhard Schmidt

IPC: H01L31/08 ,  H01L29/66 ,  H01L31/18

CPC classification number: G01K7/18 ,  H01L28/22 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1604 ,  H01L29/408 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an embodiment, a semiconductor device includes a semiconductor substrate and an amorphous semi-insulating layer on the semiconductor substrate.

Abstract translation: 根据实施例，半导体器件在半导体衬底上包括半导体衬底和非晶半绝缘层。