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1.发明申请METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR 有权在SOI绝缘体（SOI）波形上形成具有嵌入式和表面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和平面场效应晶体管的设计结构公开(公告)号：US20110204384A1
公开(公告)日：2011-08-25
申请号：US13101267
申请日：2011-05-05
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。
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2.发明授权Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权在绝缘体上硅（SOI）晶片上形成具有嵌入和刻面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构公开(公告)号：US08525186B2
公开(公告)日：2013-09-03
申请号：US13101267
申请日：2011-05-05
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。
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3.发明申请METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR 有权在SOI绝缘体（SOI）波形上形成具有嵌入式和表面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和平面场效应晶体管的设计结构公开(公告)号：US20100295127A1
公开(公告)日：2010-11-25
申请号：US12470001
申请日：2009-05-21
IPC分类号： H01L29/786 , H01L21/336 , G06F17/50
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。
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4.发明授权Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权在绝缘体上硅（S0I）晶片上形成具有嵌入式和多面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构公开(公告)号：US07951657B2
公开(公告)日：2011-05-31
申请号：US12470001
申请日：2009-05-21
IPC分类号： H01L21/84
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以便选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。
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5.发明授权Source/drain junction for high performance MOSFET formed by selective EPI process 有权通过选择性EPI工艺形成的高性能MOSFET的源极/漏极结公开(公告)号：US07932136B2
公开(公告)日：2011-04-26
申请号：US12109025
申请日：2008-04-24
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译： 在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。 源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。 通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。 这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。
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6.发明申请SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS 有权通过选择性EPI工艺形成的高性能MOSFET的源极/漏极连接公开(公告)号：US20090267149A1
公开(公告)日：2009-10-29
申请号：US12109025
申请日：2008-04-24
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译： 在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。 源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。 通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。 这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。
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公开(公告)号：US08513718B2
公开(公告)日：2013-08-20
申请号：US13419164
申请日：2012-03-13
IPC分类号： H01L29/76
CPC分类号： H01L29/7849 , H01L29/66636 , H01L29/78
摘要： A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
摘要翻译： 晶体管器件包括通过栅极电介质在半导体衬底上间隔开的栅极导体，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中该沟道区域包括栅极下方的底切区域 导体; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。
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公开(公告)号：US08216893B2
公开(公告)日：2012-07-10
申请号：US12691170
申请日：2010-01-21
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/66636 , H01L29/78
摘要： Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
摘要翻译： 公开了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：通过栅极电介质在半导体衬底上方间隔开的栅极导体，其中半导体衬底包括在栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中沟道区域包括 栅极导体下方的底切区域; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。
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公开(公告)号：US20100187578A1
公开(公告)日：2010-07-29
申请号：US12691170
申请日：2010-01-21
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7849 , H01L29/66636 , H01L29/78
摘要： Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
摘要翻译： 公开了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：通过栅极电介质在半导体衬底上方间隔开的栅极导体，其中半导体衬底包括在栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中沟道区域包括 栅极导体下方的底切区域; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。
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公开(公告)号：US20120168775A1
公开(公告)日：2012-07-05
申请号：US13419164
申请日：2012-03-13
CPC分类号： H01L29/7849 , H01L29/66636 , H01L29/78
摘要： A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
摘要翻译： 晶体管器件包括通过栅极电介质在半导体衬底上间隔开的栅极导体，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中该沟道区域包括栅极下方的底切区域 导体; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。
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