公开(公告)号：US5070444A

公开(公告)日：1991-12-03

申请号：US562255

申请日：1990-08-03

申请人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

发明人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

IPC分类号： G06F12/08

CPC分类号： G06F12/0851

摘要： In a storage system having a main storage and a buffer storage accessable by a plurality of requesters, the buffer storage comprises a buffer storage data area having a plurality of storage areas for storing a portion of data of the main storage as a copy of the main storage for each predetermind storage unit, and a buffer storage addess area for storing addresses of the predetermined storage units coresponding to the storage areas. The buffer storage address area is divided into a plurality of addres area banks each interleaved by storage unit, and the buffer storage data area is divided into a plurality of data area banks each interleaved by an access width unit.

公开(公告)号：US4949244A

公开(公告)日：1990-08-14

申请号：US148859

申请日：1988-01-27

申请人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

发明人： Kanji Kubo ,  Akio Yamamoto ,  Katsumi Takeda

IPC分类号： G06F12/08

CPC分类号： G06F12/0851

摘要： In a storage system having a main storage and a buffer storage accessable by a plurality of requesters, the buffer storage comprises a buffer storage data area having a plurality of storage areas for storing a portion of data of the main storage as a copy of the main storage for each predetermined storage unit, and a buffer storage address area for storing addresses of the predetermined storage units corresponding to the storage areas. The buffer storage address area is divided into a plurality of address area banks each interleaved by storage unit, and the buffer storage data area is divided into a plurality of data area banks each interleaved by an access width unit.

公开(公告)号：US4916604A

公开(公告)日：1990-04-10

申请号：US211451

申请日：1988-06-24

申请人： Akio Yamamoto ,  Kanji Kubo

发明人： Akio Yamamoto ,  Kanji Kubo

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0857

摘要： A cache storage apparatus used for a plurality of requestors includes a unit for detecting if consecutive requests by the same requestor have the same access line; a stack unit for storing access addresses to a cache storage unit for each requestor after a cache directory unit was searched; and a plurality of pipe lines allowing the service of plural and concurrent accesses to other than the cache directory unit. In the cache storage apparatus, if there are consecutive accesses to the same line from the same requestor, the access address to the cache storage unit for the succeeding request is not obtained by searching the cache directory unit, but the access address to the cache storage unit for the preceding request is read from the stack unit and used as the access address for the succeeding request. If there is an access request from another requestor while processing the succeeding request which does not require the search of the cache directory unit, the priviledge of using the cache directory unit is given to the access request by the other requestor to thereby allow concurrently processing a plurality of requests.

摘要翻译： 用于多个请求者的高速缓存存储装置包括用于检测同一请求者的连续请求是否具有相同访问线的单元; 堆栈单元，用于在搜索高速缓存目录单元之后，将访问地址存储到每个请求者的高速缓存存储单元; 以及允许多个并行访问的服务的多条管线，而不是高速缓存目录单元。 在高速缓存存储装置中，如果从相同的请求者连续访问同一行，则通过搜索高速缓存目录单元，而不是高速缓存存储单元的访问地址不能获得用于后续请求的高速缓存存储单元的访问地址 从堆栈单元读取上述请求的单位，并将其用作后续请求的访问地址。 如果在处理不需要搜索高速缓存目录单元的后续请求的情况下存在来自另一请求者的访问请求，则由其他请求者将访问请求赋予给高速缓存目录单元的授权，从而允许同时处理 多个请求

公开(公告)号：US5072319A

公开(公告)日：1991-12-10

申请号：US465216

申请日：1990-03-06

申请人： Toshiyuki Kohri ,  Kanji Kubo

发明人： Toshiyuki Kohri ,  Kanji Kubo

IPC分类号： G11B5/588 ,  G11B5/592 ,  G11B15/18

CPC分类号： G11B5/592 ,  G11B15/1875 ,  G11B5/588

摘要： There is provided a correction value generating means (15) which utilizes, as a correction value, the difference between a first tracking error signal provided by a first tracking error detecting means (13) and a second tracking error signal provided by a second tracking error detecting means (10) where any one of first magnetic heads (3), (4) and second magnetic heads (5), (6) fitted through electric-mechanical transducing elements (7), (8) is in a state of reproducing, but the difference between the second tracking error signal of a recorded track being currently reproduced and the second tracking error signal preceding the recorded track is used as the correction value where the first magnetic heads (3), (4) are in a state of recording while the second magnetic heads (5), (6) are in a state of reproducing, so that the correction value can be used to correct a reference signal used to drive the electric-mechanical transducing elements thereby to control the electric-mechanical transducing elements (7), (8) whereby the first magnetic heads can during the recording scan the track so as to follow a curvature thereof to accomplish a favorable editing and recording wherein, even in a magnetic tape having bent tracks differing at the start and end points of the editing and recording, neither erasure of the tracks on respective sides of a joint nor insufficient erasure occur.

摘要翻译： PCT No.PCT / JP89 / 00689。 371 1990年3月26日第 102（e）1990年3月26日PCT PCT 1989年7月7日PCT公布。 公开号WO90 / 00796 提供了一种校正值生成装置（15），其利用由第一跟踪误差检测装置（13）提供的第一跟踪误差信号和第二跟踪误差之间的差作为校正值， 信号由第二跟踪误差检测装置（10）提供，其中第一磁头（3），（4）和第二磁头（5），（6）中的任何一个通过电机转换元件（7），（8） ）处于再现状态，但是使用当前再现的记录磁道的第二跟踪误差信号与记录轨道之前的第二跟踪误差信号之间的差作为校正值，其中第一磁头（3），（ 4）处于记录状态，而第二磁头（5），（6）处于再现状态，从而可以使用校正值来校正用于驱动电机转换元件的参考信号 控制电 c-机械转换元件（7），（8），由此第一磁头可以在记录期间扫描轨道以跟随其曲率，以实现有利的编辑和记录，其中即使在具有不同于 编辑和记录的开始和结束点，不会擦除关节的相应两侧的轨迹，也不会发生不充分的擦除。

公开(公告)号：US4840396A

公开(公告)日：1989-06-20

申请号：US123870

申请日：1987-11-23

申请人： Kanji Kubo

发明人： Kanji Kubo

IPC分类号： B60G3/20

CPC分类号： B60G3/202 ,  B60G2200/141 ,  B60G2200/18 ,  B60G2200/182 ,  B60G2200/462 ,  B60G2202/12 ,  B60G2202/24 ,  B60G2204/1244 ,  B60G2204/143 ,  B60G2204/148 ,  B60G2204/422

摘要： A rear suspension system for automobiles, comprising: a trailing arm pivoted to the automobile body at its front end and to a knuckle at its rear end; a first and a second lateral links extending laterally across an upper portion and a lower portion of the knuckle and the corresponding locations of the automobile body, respectively; and a third lateral link extending laterally across an intermediate position of the knuckle, located between the upper portion and the lower portion of the knuckle and behind a central axial line of a wheel axle of the knuckle, and the corresponding location of the automobile body. The second lateral link has a substantially same length as the third lateral link. Thus, the mounting positions of the lower end of the shock absorber can be lowered, and the resistance against the changes in the toe angle and the camber angle is increased. If the first lateral link is shorter than the second lateral link, the camber angle of the outer wheel of a vehicle making a turn can become negative so as to improve the cornering limit of the automobile.

摘要翻译： 一种用于汽车的后悬挂系统，包括：在其前端处枢转到汽车车身的后臂和在其后端处的转向节; 第一和第二横向连杆横向延伸穿过转向节的上部和下部以及汽车车身的对应位置; 以及横向延伸穿过转向节的中间位置的第三横向连杆，位于转向节的上部和下部之间并且在转向节的轮轴的中心轴线之后和汽车车身的相应位置。 第二横向连杆具有与第三横向连杆大致相同的长度。 因此，减震器的下端的安装位置可以降低，并且抵抗尖角和外倾角的变化的阻力增加。 如果第一横向连杆短于第二侧向连杆，则转向车辆的外轮的外倾角可能变为负，从​​而改善汽车的转弯极限。

公开(公告)号：US4816930A

公开(公告)日：1989-03-28

申请号：US889926

申请日：1986-07-28

申请人： Kanji Kubo ,  Naoshi Usuki ,  Hiroshi Taniguchi ,  Mitsunobu Furumoto

发明人： Kanji Kubo ,  Naoshi Usuki ,  Hiroshi Taniguchi ,  Mitsunobu Furumoto

IPC分类号： G11B15/467 ,  G11B5/584

CPC分类号： G11B15/4678

摘要： A circuit for reproducing informaiton signals and four different tracking control pilot signals recorded on respective tracks on a magnetic tape and producing from the pilot signals a tracking error signal indicative of a relative positional deviation between each of a plurality of magnetic heads and each track of the tape. The circuit includes a balanced modulation circuit for successively multiplying reproductions of the pilot signals and a reference signal to produce a multiplication output signal having components corresponding to the respective pilot signals. Respective tuning circuits derive first and second signals from the multiplication output signal, having different frequency components and corresponding to different ones of the pilot signals. A level comparison circuit compares the first and second signals in level to produce a level-compared output signal whose value is indicative of the relative levels of the first and second signals, the level-compared output signal having respective portions corresponding to successive periods of reproducing signals on tracks on which different ones of the pilot signals are recorded. A further portion of this circuit time-divisionally extracts the values of levels of the level-compared output signal. A further comparator calculates the values of the differences between at least two of the extracted level values to produce the tracking error signal. The circuitry eliminates any variations in the tracking error signal which may be caused by any variations in mechanical height of the magnetic heads.

摘要翻译： 一种用于再现信息信号的电路和记录在磁带上的相应磁道上的四个不同的跟踪控制导频信号，并且从导频信号产生一个跟踪误差信号，该跟踪误差信号指示多个磁头中的每一个与每个磁头之间的相对位置偏差 胶带。 电路包括用于连续地乘以导频信号的再现和参考信号的平衡调制电路，以产生具有对应于各导频信号的分量的乘法输出信号。 相应的调谐电路从乘法输出信号中导出具有不同频率分量并对应于导频信号中的不同导频信号的第一和第二信号。 电平比较电路比较电平中的第一和第二信号以产生电平比较输出信号，其电平值表示第一和第二信号的相对电平，电平比较输出信号具有对应于连续的再现周期的各部分 在其上记录有不同导频信号的磁道上的信号。 该电路的另一部分分时提取电平比较输出信号的电平值。 另一比较器计算提取的电平值中的至少两个之间的差的值，以产生跟踪误差信号。 电路消除了可能由磁头的机械高度的任何变化引起的跟踪误差信号中的任何变化。

公开(公告)号：US4658356A

公开(公告)日：1987-04-14

申请号：US553235

申请日：1983-11-18

申请人： Kenichi Shiozaki ,  Makoto Kishi ,  Tomoatsu Yanagita ,  Kanji Kubo

发明人： Kenichi Shiozaki ,  Makoto Kishi ,  Tomoatsu Yanagita ,  Kanji Kubo

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/14 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F12/0804 ,  G06F12/1475 ,  G06F13/00

摘要： Change bits are provided in correspondence with storage information units (blocks or pages) of a storage, and indicate whether or not a "store" operation has been performed into the corresponding storage information units. The change bits are retained in a first retention device in correspondence with the storage information units, and a copy of the change bits in the first retention device is retained in a second retention device. When the store operation is performed to effect a storing of data into the storage, a control device refers to the change bit retained by the second retention device and controls updating of the change bit of the first retention device in accordance with the indication of the change bit referred to.

摘要翻译： 与存储器的存储信息单元（块或页）相对应地提供更改位，并且指示是否已经对相应的存储信息单元执行“存储”操作。 更改位与存储信息单元对应地保留在第一保持装置中，并且第一保持装置中的更改位的副本保留在第二保持装置中。 当执行存储操作以将数据存储到存储器中时，控制装置参考由第二保持装置保持的更改位，并且根据变化的指示控制第一保持装置的更改位的更新 位参考。

公开(公告)号：US4561071A

公开(公告)日：1985-12-24

申请号：US519699

申请日：1983-08-02

申请人： Noriaki Hashimoto ,  Kanji Kubo ,  Chikahiko Izumi

发明人： Noriaki Hashimoto ,  Kanji Kubo ,  Chikahiko Izumi

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C11/40

CPC分类号： G06F12/1054

摘要： This storage system is designed to refer to a translation lookaside buffer, a buffer address array and a buffer storage in parallel. The translation lookaside buffer translates a logical address requesting memory access into a real address. The buffer storage retains part of the data retained in blocks by main storage and outputs data from M blocks in accordance with the logical address to M aligners. The buffer address array retains the addresses in MS of the data stored in each of the blocks in the buffer storage, and outputs M addresses in accordance with the logical address. A comparator compares the real addresses from the translation lookaside buffer with the addresses from the buffer address array, selects one of the outputs from the aligners, and transfers that output to a processor.

摘要翻译： 该存储系统被设计为并行地指代翻译后备缓冲器，缓冲器地址阵列和缓冲存储器。 翻译后备缓冲器将请求存储器访问的逻辑地址转换成真实地址。 缓冲存储器通过主存储保留保留在块中的数据的一部分，并且根据逻辑地址向M个对准器输出来自M个块的数据。 缓冲器地址阵列保存缓冲存储器中存储在每个块中的数据的MS中的地址，并且根据逻辑地址输出M个地址。 比较器将来自翻译后备缓冲器的实际地址与来自缓冲器地址阵列的地址进行比较，从对准器中选择一个输出，并将该输出传送到处理器。

公开(公告)号：US4390906A

公开(公告)日：1983-06-28

申请号：US255348

申请日：1981-04-17

申请人： Mitsunobu Furumoto ,  Osahiko Yano ,  Hiroshi Taniguchi ,  Kanji Kubo ,  Masamitsu Ohtsu

发明人： Mitsunobu Furumoto ,  Osahiko Yano ,  Hiroshi Taniguchi ,  Kanji Kubo ,  Masamitsu Ohtsu

IPC分类号： G11B20/00 ,  H04N5/782 ,  H04N5/7826 ,  H04N5/928 ,  H04N5/78

CPC分类号： H04N5/928 ,  H04N5/782 ,  H04N5/78263

摘要： A two speed or multi-speed video tape recorder of the conventional helical scan type in which the audio signal is capable of being recorded as a time compressed signal at one end of each helical video scan, or alternatively, in conventional longitudinal fashion by means of a stationary magnetic head engaging one edge of the tape.At low tape transport speeds, improved bandwidth (and therefore sound fidelity) is obtained by use of the time compression technique; while at higher transport speeds, there are advantages in utilizing the stationary audio head.Circuitry is provided to automatically utilize the time compression technique at lower tape transport speeds and the stationary head longitudinal recording technique at higher tape transport speeds. A pilot or cue signal is recorded on the tape, to automatically control the reproduction circuitry so that both types of recording methods can be interchanged on the same magnetic tape, with the reproducing circuitry switching accordingly between the two modes, as required.

摘要翻译： 常规螺旋扫描类型的双速或多速录像机，其中音频信号能够在每个螺旋视频扫描的一端被记录为时间压缩信号，或者以常规的纵向方式通过 与磁带的一个边缘接合的固定磁头。 在低磁带传输速度下，通过使用时间压缩技术可以获得改进的带宽（因而声音保真度）; 而在较高的传输速度下，利用固定音频头具有优点。 提供电路以在较低的磁带传输速度下自动利用时间压缩技术，并以更高的磁带传输速度自动利用固定磁头纵向记录技术。 导频或提示信号被记录在磁带上，以便自动控制再现电路，使得两种类型的记录方法可以在同一磁带上互换，根据需要，再现电路在两种模式之间相应地切换。

公开(公告)号：US4251859A

公开(公告)日：1981-02-17

申请号：US957688

申请日：1978-11-06

申请人： Tsugio Momose ,  Akira Fujita ,  Kanji Kubo

发明人： Tsugio Momose ,  Akira Fujita ,  Kanji Kubo

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/38

CPC分类号： G06F9/3836

摘要： A data processing system, for executing each instruction, by carrying out a plurality of successive partial processing operations, begins to process the first partial processing operation of an instruction succeeding a defeat overlap instruction before execution of the defeat overlap instruction is finished in response to the detection that a predetermined number of machine cycles is further required for the complete execution of the defeat overlap instruction.

摘要翻译： 用于通过执行多个连续的部分处理操作来执行每个指令的数据处理系统开始处理在执行失败重叠指令之前的失败重叠指令之后的指令的第一部分处理操作，以响应于 检测到完全执行失败重叠指令还需要预定数量的机器周期。