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1.发明授权公开(公告)号：US08139699B2
公开(公告)日：2012-03-20
申请号：US12185688
申请日：2008-08-04
IPC分类号： H04L7/00
CPC分类号： H04L27/2647
摘要： A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.
摘要翻译： 用于多个基带数字化信号流的前导码检测器具有多个前同步码处理器，每个前同步码处理器耦合到输入并产生输出。 每个前导处理器具有耦合到第一延迟的输入，第一延迟的输出耦合到产生输出的第二延迟。 第一和第二延迟基本上等于前导码部分。 第一乘法器产生来自第二延迟输出的共轭输出的输出和第一延迟输出。 第二乘法器产生来自共轭第一延迟输出和输入流的输出。 第一乘法器和第二乘法器输出在一个间隔上累积，并且累加器的复数输出形成一个幅度，由此产生每个前导码处理器的输出。 将前同步码处理器的输出相加并与阈值进行比较，以产生前导码检测。
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公开(公告)号：US08005179B2
公开(公告)日：2011-08-23
申请号：US12185648
申请日：2008-08-04
IPC分类号： H03D1/04
CPC分类号： H04L27/2647
摘要： A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.
摘要翻译： 用于多个基带数字化信号流的前导码检测器具有多个前同步码处理器，每个前同步码处理器耦合到输入并产生输出。 每个前导处理器具有耦合到第一延迟的输入，第一延迟的输出耦合到产生输出的第二延迟。 第一和第二延迟基本上等于前导码部分。 第一乘法器产生来自第二延迟输出的共轭输出的输出和第一延迟输出。 第二乘法器产生来自共轭第一延迟输出和输入流的输出。 第一乘法器和第二乘法器输出在一个间隔上累积，并且累加器的复数输出形成一个幅度，由此产生每个前导码处理器的输出。 将前同步码处理器的输出相加并与阈值进行比较，以产生前导码检测。
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公开(公告)号：US20100027718A1
公开(公告)日：2010-02-04
申请号：US12185648
申请日：2008-08-04
IPC分类号： H04L27/06
CPC分类号： H04L27/2647
摘要： A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.
摘要翻译： 用于多个基带数字化信号流的前导码检测器具有多个前同步码处理器，每个前同步码处理器耦合到输入并产生输出。 每个前导处理器具有耦合到第一延迟的输入，第一延迟的输出耦合到产生输出的第二延迟。 第一和第二延迟基本上等于前导码部分。 第一乘法器产生来自第二延迟输出的共轭输出的输出和第一延迟输出。 第二乘法器产生来自共轭第一延迟输出和输入流的输出。 第一乘法器和第二乘法器输出在一个间隔上累积，并且累加器的复数输出形成一个幅度，由此产生每个前导码处理器的输出。 将前同步码处理器的输出相加并与阈值进行比较，以产生前导码检测。
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公开(公告)号：US20190244418A1
公开(公告)日：2019-08-08
申请号：US16269270
申请日：2019-02-06
申请人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
CPC分类号： G06T15/80 , G06F9/50 , G06F9/5011 , G06T1/20 , G06T5/20
摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
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5.发明授权Analog to digital converter bit width and gain controller for a wireless receiver 有权用于无线接收器的模数转换器位宽和增益控制器公开(公告)号：US08073085B1
公开(公告)日：2011-12-06
申请号：US11825832
申请日：2007-07-07
IPC分类号： H04L27/08
CPC分类号： H04L27/2647 , H04L27/2613
摘要： A gain controller for a wireless communication system sets the receiver gain during the initial time duration of a preamble, and for each subsequent symbol computes a new gain value, which is applied at the end of each symbol. An analog to digital converter resolution controller sets the resolution of the ADC to a high resolution during a preamble interval and a first symbol interval, and to a comparatively lower resolution thereafter until the end of the frame. When a new zone is entered, the first symbol of the new zone is sampled at a higher resolution than the subsequent symbols.
摘要翻译： 用于无线通信系统的增益控制器在前导码的初始持续时间期间设置接收机增益，并且对于每个后续符号计算在每个符号的末尾应用的新的增益值。 模数转换器分辨率控制器在前导码间隔和第一符号间隔期间将ADC的分辨率设置为高分辨率，并且之后到相对较低的分辨率直到帧结束。 当输入新区域时，新区域的第一个符号以比后续符号更高的分辨率进行采样。
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公开(公告)号：US20100138632A1
公开(公告)日：2010-06-03
申请号：US12327395
申请日：2008-12-03
申请人： Phanimithra Gangalakurti , Karthik Vaidyanathan , Partha Sarathy Murali , InduShekhar Ayyalasomayajula
发明人： Phanimithra Gangalakurti , Karthik Vaidyanathan , Partha Sarathy Murali , InduShekhar Ayyalasomayajula
CPC分类号： G06F7/4818
摘要： A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.
摘要翻译： CORDIC处理器具有多个级，每个级具有X输入，Y输入，符号输入，符号输出，X输出，Y输出，具有ROTATE或VECTOR值的模式控制输入，以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位，通过移位X个输入k次来产生输出的第二移位;当模式控制时，具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时，输入为ROTATE和Y输入的符号，形成第一移位输出和多路复用器输出的乘积的第一乘法器，形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出，从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。
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公开(公告)号：US20090304103A1
公开(公告)日：2009-12-10
申请号：US12134215
申请日：2008-06-06
IPC分类号： H04B7/06
CPC分类号： H04B7/0443
摘要： A transmit power allocation method for computing a transmit beamforming W matrix for a N streams of data, the method has a first step of measuring a receive channel characteristic H matrix, a second step of decomposing the H matrix into a U matrix which is formed from the left eigenvectors of the H matrix, an Σ matrix which is a diagonal matrix formed from the square roots of the eigenvalues of said H matrix and re-ordered by strength, and a VT matrix with rows comprising the right eigenvectors of H, such that UΣVT=H. The transmit beamforming W matrix is then formed from the re-ordered V matrix of the previous decomposition. Optional waterfilling methods for a plurality of subcarriers may then be done using either a minimum mean square error, an optimal signal to noise ratio, or any other waterfilling method which optimizes a desired metric, such as signal to noise ratio or minimum mean square error.
摘要翻译： 一种用于计算N个数据流的发送波束形成W矩阵的发送功率分配方法，所述方法具有测量接收信道特性H矩阵的第一步骤，将所述H矩阵分解成U矩阵的第二步骤，所述U矩阵由 H矩阵的左特征向量，作为由所述H矩阵的特征值的平方根并由强度重新排序的对角矩阵的Sigma矩阵，以及包括H的右特征向量的行的VT矩阵，使得 USigmaVT = H。 然后从先前分解的重排V矩阵形成发射波束形成W矩阵。 然后可以使用最小均方误差，最佳信噪比或者优化所需度量（例如信噪比或最小均方误差）的任何其它灌水方法来完成多个子载波的可选填埋方法。
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公开(公告)号：US20130257891A1
公开(公告)日：2013-10-03
申请号：US13628247
申请日：2012-09-27
申请人： Rahul P. Sathe , Tim Foley , Karthik Vaidyanathan
发明人： Rahul P. Sathe , Tim Foley , Karthik Vaidyanathan
IPC分类号： G09G5/02
CPC分类号： G06T15/005 , G06T1/60 , G06T17/20
摘要： In accordance with some embodiments, domain shader and/or tessellator operations can be eliminated when they are redundant. By using a corner cache, a check can determine whether a given corner, be it a vertex or a quadrilateral corner, has already been evaluated in the domain shader and/or tessellator and if so, the result of the previous operation can be reused instead of performing unnecessary invocations that may increase power consumption or reduce speed.
摘要翻译： 根据一些实施例，当它们是冗余时，可以消除域着色器和/或细分器操作。 通过使用角落缓存，检查可以确定在域着色器和/或细分器中是否已经评估了一个给定的角点（无论是顶点还是四边形角），如果是，则可以重新使用先前操作的结果 执行可能增加功耗或降低速度的不必要的调用。
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公开(公告)号：US08259786B2
公开(公告)日：2012-09-04
申请号：US12368431
申请日：2009-02-10
IPC分类号： H03H7/30
CPC分类号： H04L27/2647 , H04L25/022 , H04L25/03159
摘要： A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.
摘要翻译： 具有有限脉冲响应（FIR）的信道平滑滤波器具有控制器，其以这样的方式从FFT存储器中读取并行取样数据，以产生偶函数，该样本数据应用于伴有前置码符号的前同步码均衡器， 零，所述前导码输出耦合到三个滤波器处理器，每个滤波器处理器具有四个滤波器引擎，其输出相加，所述信道平滑滤波器产生寄存器输出，耦合到具有作为输入的加法器的寄存器输入：第一滤波器处理器被移位 由四个，第二个滤波器处理器移位两个，第三个滤波器处理器和寄存器输出。 边缘滤波器和中央滤波器的系数以零符号移位（ZSS）格式提供，并且通过使用规范有符号数字（CSD）算法选择系数，通道平滑FIR滤波器不需要乘法器。
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公开(公告)号：US08223906B2
公开(公告)日：2012-07-17
申请号：US12197234
申请日：2008-08-23
CPC分类号： H04L27/2647 , H04L27/2626
摘要： A transmit filter for a stream of OFDM symbols has a remapper, Infinite Impulse Response (IIR) filter and a controller, the transmit filter operating on a stream of OFDM symbols. The transmit filter accepts symbols to be transmitted, the re-mapper re-orders them, the IIR filters the re-ordered stream, and a controller provides an output by rearranging the filtered symbols. The incoming symbol stream contains a series of symbols, each followed by a guard interval, where each guard interval has a first Tg symbol interval, and a second Tg symbol interval, the remapper generating a re-ordered stream having a first Tg symbol interval, a second Tg symbol interval and the symbol, the output of the IIR filter thereby generating a filtered first Tg symbol, a filtered second Tg symbol, and a filtered symbol, and the controller forms the transmit output by discarding the filtered first Tg symbol and outputting, in sequence, the filtered second Tg symbol, the filtered symbol, and a copy of the filtered second Tg symbol. The filtered second Tg symbol may be saved into a local buffer at the time it is initially output for use following the current symbol.
摘要翻译： 用于OFDM符号流的发射滤波器具有再映射器，无限脉冲响应（IIR）滤波器和控制器，所述发射滤波器在OFDM符号流上操作。 发送过滤器接受要发送的符号，重新映射器重新命令它们，IIR对重新排序的流进行滤波，并且控制器通过重排排序的滤波符号来提供输出。 输入符号流包含一系列符号，每个符号后面是保护间隔，其中每个保护间隔具有第一Tg符号间隔和第二Tg符号间隔，再生映射器产生具有第一Tg符号间隔的重排序流， 第二Tg符号间隔和符号，IIR滤波器的输出，从而产生滤波后的第一Tg符号，滤波后的第二Tg符号和滤波符号，并且控制器通过丢弃滤波后的第一Tg符号并输出 按照顺序，滤波后的第二Tg符号，滤波后的符号和滤波的第二Tg符号的副本。 经滤波的第二Tg符号可以在其最初输出之后被保存到本地缓冲器中以便在当前符号之后使用。
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