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公开(公告)号：US06658154B2
公开(公告)日：2003-12-02
申请号：US09365865
申请日：1999-08-03
IPC分类号： G06K946
CPC分类号： G06T1/60 , H04N19/176 , H04N19/423 , H04N19/61 , H04N19/90
摘要： A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.
摘要翻译： 存储器控制部分12分别循环地将时隙分配给缓冲存储器部分21至25，并且在每个时隙中控制对应的缓冲存储器部分和同步RAM 11之间的访问。确定时隙，同时假定访问 同步RAM是最严重的。 数字中的[（一条水平扫描线上的像素数）/ 256]的时隙组在虚拟的一个水平扫描周期中生成，其中[]表示括号中的数字的整数部分。 对于其数据量根据压缩因子而变化的缓冲存储器22，可以使时隙终点可变，或者可以通过中断产生时隙作为例外。
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2.发明授权One-chip first-in first-out memory device having matched write and read operations 失效具有匹配的写入和读取操作的单芯片先进先出的存储器件
公开(公告)号：US5220529A
公开(公告)日：1993-06-15
申请号：US747047
申请日：1991-08-19
摘要： A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read address upon the first-in first-out memory device. The write address is cleared by a write reset signal, and the read address is cleared by a read reset signal. A delay circuit is provided to coincide an effective timing of the write reset signal in the memory cell array with that of the read reset signal in the memory cell array.
摘要翻译： 通过在先进先出存储器件中使用顺序递增的写入地址来执行写入操作，并且通过在先进先出存储器件中使用顺序递增的读取地址来执行读取操作。 写入地址由写入复位信号清零，读取地址由读取复位信号清零。 提供延迟电路以将存储单元阵列中的写入复位信号的有效定时与存储单元阵列中的读取复位信号的有效定时重合。
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3.发明授权Color image display control apparatus with correction of phase difference in sampling clock 失效具有采样时钟相位差校正的彩色图像显示控制装置
公开(公告)号：US5043799A
公开(公告)日：1991-08-27
申请号：US369051
申请日：1989-06-20
CPC分类号： H04N9/64
摘要： A color image display control apparatus for receiving a composite color picture signal and processing color image data included in the signal. A color picture signal in an analog form included in the composite color picture signal is converted to a digital form by sampling the analog signal at each cycle of a sampling clock, in and analog to digital converter. The digital image data is processed in a digital image processing circuit. Processed digital data is converted to analog data in a digital to analog converter. Information regarding a phase difference between the sampling clock and each horizontal synchronizing signal in the composite color picture signal is obtained. According to the information, a digital image data in a line corresponding to each horizontal synchronizing signal, which was sampled by the sampling clock, is modified so that the influence of the above phase difference on a displayed image of the processed image data is corrected.
摘要翻译： 一种彩色图像显示控制装置，用于接收复合彩色图像信号并处理包括在该信号中的彩色图像数据。 包含在复合彩色图像信号中的模拟形式的彩色图像信号通过在采样时钟和模数转换器的每个周期采样模拟信号而被转换为数字形式。 数字图像数据在数字图像处理电路中进行处理。 处理的数字数据被转换成数模转换器中的模拟数据。 获得关于合成彩色图像信号中的采样时钟和每个水平同步信号之间的相位差的信息。 根据该信息，修改与由采样时钟采样的每个水平同步信号相对应的行中的数字图像数据，以便校正上述相位差对经处理图像数据的显示图像的影响。
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4.发明授权Method and apparatus for detecting a phase difference between two digital signals 失效用于检测两个数字信号之间的相位差的方法和装置
公开(公告)号：US4963817A
公开(公告)日：1990-10-16
申请号：US372452
申请日：1989-06-28
CPC分类号： G01R25/00
摘要： In an apparatus for detecting a phase difference between two digital signals including an n stage delay circuit, an n bit register connected to the n stage delay circuit, a signal encoding means connected to the n bit register, and a compensation circuit connected to the encoder, a test signal is applied to the delay circuit first and two different delayed data are obtained by applying a reference signal to the n bit register twice, the delay characteristics of the delay circuit is calculated by using two different data and the period time of the two reference signals, then a signal to be subjected to phase difference detection is applied to the delay circuit to obtain delayed data by applying a reference signal to the n bit register, the delayed data is compensated at the compensating circuit by using the delay characteristics of the delay circuit. Thus, an accurate phase difference between two digital signals is obtained.
摘要翻译： 在用于检测包括n级延迟电路的两个数字信号，连接到n级延迟电路的n位寄存器，连接到n位寄存器的信号编码装置以及连接到编码器的补偿电路的两个数字信号之间的相位差检测装置中， 首先将测试信号施加到延迟电路，并通过将参考信号施加到n位寄存器两次来获得两个不同的延迟数据，延迟电路的延迟特性通过使用两个不同的数据和 两个参考信号，则通过向n位寄存器施加参考信号，将延迟电路施加到延迟电路上以进行相位差检测的信号以获得延迟的数据，在补偿电路上通过使用延迟特性 延时电路。 因此，获得两个数字信号之间的精确相位差。
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公开(公告)号：US20080151677A1
公开(公告)日：2008-06-26
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。
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公开(公告)号：US20100146201A1
公开(公告)日：2010-06-10
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
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公开(公告)号：US20080181027A1
公开(公告)日：2008-07-31
申请号：US12000952
申请日：2007-12-19
申请人： Takahiro Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiro Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
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公开(公告)号：US07729200B2
公开(公告)日：2010-06-01
申请号：US12000840
申请日：2007-12-18
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
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公开(公告)号：US20090027988A1
公开(公告)日：2009-01-29
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储器单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。
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公开(公告)号：US20080189467A1
公开(公告)日：2008-08-07
申请号：US12000840
申请日：2007-12-18
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/00
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
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