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公开(公告)号：US20070037403A1
公开(公告)日：2007-02-15
申请号：US11161599
申请日：2005-08-09
申请人： Kaushik Chanda , Lawrence Clevenger , Andrew Cowley , Jason Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence Clevenger , Andrew Cowley , Jason Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。
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2.发明申请STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS 有权用于监测导电互连的应力诱导降解的结构和方法公开(公告)号：US20070115018A1
公开(公告)日：2007-05-24
申请号：US11163948
申请日：2005-11-04
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。
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3.发明申请公开(公告)号：US20080107149A1
公开(公告)日：2008-05-08
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。
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4.发明申请公开(公告)号：US20060281338A1
公开(公告)日：2006-12-14
申请号：US11160213
申请日：2005-06-14
申请人： Kaushik Chanda , Hazara Rathore , Paul McLaughlin , Robert Edwards , Lawrence Clevenger , Andrew Cowley , Chih-Chao Yang , Conrad Barile
发明人： Kaushik Chanda , Hazara Rathore , Paul McLaughlin , Robert Edwards , Lawrence Clevenger , Andrew Cowley , Chih-Chao Yang , Conrad Barile
IPC分类号： H01L21/00
CPC分类号： H01L22/14 , G01R31/2642 , G01R31/2831
摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.
摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个绝缘击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。
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公开(公告)号：US07749778B2
公开(公告)日：2010-07-06
申请号：US11619307
申请日：2007-01-03
IPC分类号： H01L21/66
CPC分类号： G01R31/2858 , H01L22/14 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.
摘要翻译： 一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查 以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。
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公开(公告)号：US20080160656A1
公开(公告)日：2008-07-03
申请号：US11619307
申请日：2007-01-03
CPC分类号： G01R31/2858 , H01L22/14 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.
摘要翻译： 一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查 以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。
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7.发明申请METHOD AND STRUCTURE OF FORMING AN INTERCONNECT INCLUDING A DIELECTRIC CAP HAVING A TENSILE STRESS 有权形成互连的方法和结构，包括具有拉伸应力的电介质盖公开(公告)号：US20070063348A1
公开(公告)日：2007-03-22
申请号：US11162666
申请日：2005-09-19
申请人： Chih-Chao Yang , Kaushik Chanda , Lawrence Clevenger , Yun-Yu Wang , Daewon Yang
发明人： Chih-Chao Yang , Kaushik Chanda , Lawrence Clevenger , Yun-Yu Wang , Daewon Yang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
摘要翻译： 提供了互连结构及其制造方法。 互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。 电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。
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公开(公告)号：US20060234497A1
公开(公告)日：2006-10-19
申请号：US11107074
申请日：2005-04-15
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
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公开(公告)号：US20060292852A1
公开(公告)日：2006-12-28
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。
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公开(公告)号：US20080014744A1
公开(公告)日：2008-01-17
申请号：US11860602
申请日：2007-09-25
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
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