中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.019 seconds)

    Method of manufacturing semiconductor device
    1.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06924176B2

    公开(公告)日：2005-08-02

    申请号：US10103696

    申请日：2002-03-25

    Applicant: Toru Yoshie ,  Kazuhide Abe ,  Yusuke Harada

    Inventor： Toru Yoshie ,  Kazuhide Abe ,  Yusuke Harada

    IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/525 ,  H01L21/82 ,  H01L21/26 ,  H01L21/326

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.

    Abstract translation: 形成在半导体衬底上的绝缘层上的导电层通过穿过绝缘层并到达半导体衬底的贯穿部连接到半导体衬底。 在导电层通过贯通部分电连接到半导体衬底的状态下，在导电层上进行使用等离子体蚀刻的图案化工艺，从而形成导电路径。 在形成导电路径之后，在衬底或导电路径上进行加热处理，以便通过与其接触的通孔部分和半导体衬底之间的反应而断开通孔部分和衬底之间的电连接 。

    Method of forming CVD titanium film
    2.
    发明授权
    Method of forming CVD titanium film 有权
    形成CVD钛膜的方法

    公开(公告)号：US06767812B2

    公开(公告)日：2004-07-27

    申请号：US09984383

    申请日：2001-10-30

    Applicant: Kazuhide Abe ,  Yusuke Harada

    Inventor： Kazuhide Abe ,  Yusuke Harada

    IPC: H01L2128

    CPC classification number: C23C16/0272 ,  C23C16/14

    Abstract: Before deposition of a CVD titanium film on a cobalt silicide layer, an element which reacts with titanium is provided in the cobalt silicide layer in advance. Thereafter, the CVD titanium film is deposited on the cobalt silicide using a titanium tetrachloride gas.

    Abstract translation: 在将CVD钛膜沉积在硅化钴层上之前，预先在钴硅化物层中提供与钛反应的元素。 此后，使用四氯化钛气体将CVD钛膜沉积在硅化钴上。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07176577B2

    公开(公告)日：2007-02-13

    申请号：US11010339

    申请日：2004-12-14

    Applicant: Yusuke Harada

    Inventor： Yusuke Harada

    IPC: H01L23/532

    CPC classification number: H01L21/76807 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the fist conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

    Abstract translation: 半导体器件由具有通孔的第一绝缘层构成; 包括第一导电层，第一阻挡层和第一主互连的第一互连，以及连接到第一导电层和第一阻挡层之一的第二互连。 因此，半导体装置可以避免由于引起电迁移而使第一主配线的Cu从连接到第二互连的部分转移的问题，连接部分变成空隙，并且第一互连与第二互连断开。

    Method of manufacturing a semiconductor device
    6.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06706645B2

    公开(公告)日：2004-03-16

    申请号：US10228083

    申请日：2002-08-27

    Applicant: Tomoyuki Morita ,  Yusuke Harada

    Inventor： Tomoyuki Morita ,  Yusuke Harada

    IPC: H01L21469

    CPC classification number: H01L21/76856 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76877

    Abstract: A method of manufacturing a semiconductor device, according to the present invention comprises a step for forming an insulating film over a semiconductor wafer and thereafter subjecting the same to photolithography and etching to thereby define a contact hole, a step for forming an adhesive layer over the insulating film with the contact hole defined therein, a step for placing the interior of a processing chamber under an atmosphere uncontaining oxygen and subjecting the adhesive layer to heat treatment, a step for setting the temperature of the semiconductor wafer to less than or equal to a temperature equivalent to energy of such an extent as to cut the bonding between atoms which form the adhesive layer and thereafter taking the semiconductor wafer out of the processing chamber, and a step for forming an embedding film to be embedded in the contact hole.

    Abstract translation: 根据本发明的制造半导体器件的方法包括在半导体晶片上形成绝缘膜，然后对其进行光刻和蚀刻从而限定接触孔的步骤，用于在其上形成粘合剂层的步骤 具有限定在其中的接触孔的绝缘膜，用于将处理室的内部放置在不含氧气氛并对粘合剂层进行热处理的步骤，将半导体晶片的温度设定为小于或等于 温度等于能够切割形成粘合剂层的原子之间的接合，然后将半导体晶片从处理室中取出的程度的能量，以及形成嵌入在接触孔中的嵌入膜的步骤。

    Semiconductor device having damascene interconnection structure that prevents void formation between interconnections
    10.
    发明授权
    Semiconductor device having damascene interconnection structure that prevents void formation between interconnections 有权
    具有防止互连之间的空隙形成的镶嵌互连结构的半导体器件

    公开(公告)号：US07777337B2

    公开(公告)日：2010-08-17

    申请号：US10397369

    申请日：2003-03-27

    Applicant: Yusuke Harada

    Inventor： Yusuke Harada

    IPC: H01L23/528

    CPC classification number: H01L21/76807 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a first insulating layer having a through hole; a first interconnection having a first conductive layer, a first barrier layer, and a first main interconnection; and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, a problem wherein copper in the first main interconnection transfers from a connection portion thereof to the second interconnection due to electromigration, so that a void is formed at the connected portion resulting in the first interconnection being disconnected from the second interconnection, can be prevented.

    Abstract translation: 半导体器件包括具有通孔的第一绝缘层; 具有第一导电层，第一阻挡层和第一主互连的第一互连; 以及连接到第一导电层和第一阻挡层之一的第二互连。 因此，可以防止第一主配线中的铜由于电迁移而从其连接部分转移到第二互连的问题，从而在连接部分处形成导致第一互连与第二互连断开的空隙，可以防止 。

Patent Agency Ranking