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    Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method
    2.
    发明授权
    Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method 有权
    具有存储单元的半导体器件，写入或从存储器单元读取的方法以及半导体器件制造方法

    公开(公告)号：US08675385B2

    公开(公告)日：2014-03-18

    申请号：US13067773

    申请日：2011-06-24

    申请人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

    发明人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

    IPC分类号： G11C17/08

    CPC分类号： H01L27/101 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

    摘要翻译： 第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。 第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。 第二电极耦合到第一电极。 控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到 一个字线。 第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。 第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。

    Semiconductor device with common contact coupling gate wiring integrated with gate electrode of antifuse to diffusion layer
    3.
    发明授权
    Semiconductor device with common contact coupling gate wiring integrated with gate electrode of antifuse to diffusion layer 失效
    具有公共接触耦合栅极布线的半导体器件与反熔丝扩散层的栅电极集成

    公开(公告)号：US08530949B2

    公开(公告)日：2013-09-10

    申请号：US13250516

    申请日：2011-09-30

    申请人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda ,  Kiyokazu Ishige

    发明人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda ,  Kiyokazu Ishige

    IPC分类号： H01L29/76 ,  H01L29/78

    CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.

    摘要翻译： 即使利用确定电极中是否有电荷的方法，内部书面信息也无法分析的反熔丝。 反熔丝包括栅极绝缘膜，栅电极和第一扩散层。 第二扩散层通过器件隔离膜从第一扩散层隔离，并且是与第一扩散层相同的导电类型。 栅极布线形成为与栅极电极一体化的部件，并且在器件隔离膜上延伸。 常见的接触将栅极布线耦合到第二扩散层。 栅电极由掺杂有与第一扩散层相同导电类型的杂质的多晶硅等半导体材料构成。 第二扩散层仅耦合到公共接触。

    Semiconductor memory device and antifuse programming method
    5.
    发明授权
    Semiconductor memory device and antifuse programming method 有权
    半导体存储器件和反熔丝编程方法

    公开(公告)号：US08982648B2

    公开(公告)日：2015-03-17

    申请号：US13193186

    申请日：2011-07-28

    申请人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda

    发明人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda

    IPC分类号： G11C7/00 ,  G11C17/18

    CPC分类号： G11C17/18

    摘要： An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.

    摘要翻译： 由NMOS晶体管或NMOS电容器构成的反熔丝包括耦合到栅电极的第一端子，耦合到扩散层的第二端子和介于栅极电极和扩散层之间的栅极绝缘膜。 编程电路包括具有第一电流驱动能力并执行第一编程操作的第一编程电路和具有大于第一电流驱动能力的第二电流驱动能力的第二编程电路，并且执行第二编程操作以跟随第一编程操作 。 在第一编程操作中，第一编程电路通过在第一端子和第二端子之间施加第一编程电压来分解栅极绝缘膜。 在第二编程操作中，第二编程电路在第一端子和第二端子之间施加低于第一编程电压的第二编程电压。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09111934B2

    公开(公告)日：2015-08-18

    申请号：US13137032

    申请日：2011-07-15

    申请人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    发明人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    IPC分类号： H01L23/52 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

    摘要翻译： 半导体器件包括电熔丝和用于向电熔丝施加电压的第一和第二大面积布线。 电熔丝包括熔丝单元，其包括上层熔丝布线，下层熔丝布线和连接上层熔丝布线和下层熔丝布线的布线，上层引出布线 连接上层熔丝布线和第一大面积布线并具有弯曲图案，以及连接下层熔丝布线和第二大面积布线并具有弯曲图案的下层引出布线。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08080861B2

    公开(公告)日：2011-12-20

    申请号：US12588202

    申请日：2009-10-07

    申请人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    发明人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.

    摘要翻译： 半导体器件包括电熔丝和用于向电熔丝施加电压的第一和第二大面积布线。 电熔丝包括熔丝单元，其包括上层熔丝布线，下层熔丝布线和连接上层熔丝布线和下层熔丝布线的布线，上层引出布线 连接上层熔丝布线和第一大面积布线并具有弯曲图案，以及连接下层熔丝布线和第二大面积布线并具有弯曲图案的下层引出布线。

    Method of manufacturing semiconductor device and semiconductor device
    9.
    发明授权
    Method of manufacturing semiconductor device and semiconductor device 失效
    制造半导体器件和半导体器件的方法

    公开(公告)号：US08213209B2

    公开(公告)日：2012-07-03

    申请号：US12826100

    申请日：2010-06-29

    申请人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    发明人： Hiroshi Tsuda ,  Yoshitaka Kubota ,  Hiromichi Takaoka

    IPC分类号： G11C5/00 ,  G11C17/18 ,  G11C8/00 ,  H01L23/52 ,  H01L21/336

    CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.

    摘要翻译： 在制造半导体器件的方法中，提取形成在半导体晶片上的元素特性提取图案的元素性质作为与元素特性提取图案对应的电流控制元件的元素特性。 基于所提取的元件特性，设置在半导体晶片上的节点之间形成对电流控制元件的供给能量。 设定的供给能量被提供给电流控制元件，以通过由电流控制元件击穿的装置不可逆地控制节点之间的电连接。

    Semiconductor device
    10.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20100096724A1

    公开(公告)日：2010-04-22

    申请号：US12588223

    申请日：2009-10-08

    申请人： Yoshitaka Kubota ,  Hiromichi Takaoka ,  Hiroshi Tsuda

    发明人： Yoshitaka Kubota ,  Hiromichi Takaoka ,  Hiroshi Tsuda

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device (200) includes an electric fuse (100) including: an upper layer fuse interconnect (112) formed on a substrate (not shown); a lower layer fuse interconnect (122); and a via (130) which is connected to one end of the upper layer fuse interconnect (112) and connects the upper layer fuse interconnect (112) and the lower layer fuse interconnect (122). The upper fuse interconnect (112) includes a width varying region (118) having a small interconnect width on a side of the one end.

    摘要翻译： 半导体器件（200）包括电熔丝（100），包括：形成在衬底（未示出）上的上层熔丝互连（112）; 下层熔丝互连（122）; 以及连接到上层熔丝互连（112）的一端并连接上层熔丝互连（112）和下层熔丝互连（122）的通孔（130）。 上部熔丝互连（112）包括在一端的一侧具有小互连宽度的宽度变化区（118）。