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公开(公告)号：US07480875B2
公开(公告)日：2009-01-20
申请号：US11312370
申请日：2005-12-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.
摘要翻译： 在优化半导体集成电路的必要电容时，可以通过在动态地考虑电池激活率的同时优化IR降（电压降），以更高的精度实现电容优化。 换句话说，在估计插入的电源电容以抑制电源的电压波动时，通过在考虑电路中的单元激活率的同时通过减少所需的电容分量作为整体来减少面积，或者通过选择 仅在单元操作定时的估计之后补充电源波动较大的时间部分所需的电容。 此外，可以在设计的早期的短时间内通过在电容估计时使用布线负载模型来进行该过程。
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公开(公告)号：US20060143585A1
公开(公告)日：2006-06-29
申请号：US11312370
申请日：2005-12-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.
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3.发明授权公开(公告)号：US07225418B2
公开(公告)日：2007-05-29
申请号：US10863231
申请日：2004-06-09
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Nobufusa Iwanishi , Naoki Amekawa , Masaaki Hirata , Shouzou Hirano
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G01R31/31928
摘要： There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.
摘要翻译： 包含通过基于电路信息计算电源端子处的半导体集成电路的每个实例的电压波形并分析各实例的电压波形来形成电压波形信息的步骤，通过以下步骤形成电压抽象信息： 抽取电压波形信息，以及基于电压抽象信息计算实例的延迟值的步骤。
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4.发明申请Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same 审中-公开分析半导体集成电路装置的运行方法，使用的分析装置以及使用其的优化设计方法公开(公告)号：US20060091550A1
公开(公告)日：2006-05-04
申请号：US11231810
申请日：2005-09-22
IPC分类号： H01L23/52
CPC分类号： G06F17/5031
摘要： In a method of analyzing a power noise based on the circuit information of a semiconductor integrated circuit device, the power noise is analyzed in consideration of the influence of the impedance of a substrate. Consequently, the impedance of the substrate which has not been conventionally considered is taken into consideration. Thus, precision in the analysis can be enhanced more greatly.
摘要翻译： 在基于半导体集成电路器件的电路信息分析功率噪声的方法中，考虑到衬底的阻抗的影响来分析功率噪声。 因此，考虑到未经常考虑的基板的阻抗。 因此，分析的精度可以更大的提高。
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5.发明申请Substrate noise analyzing method for semiconductor integrated circuit, semiconductor integrated circuit, and substrate noise analyzing device for semiconductor integrated circuit 审中-公开半导体集成电路的基板噪声分析方法，半导体集成电路和半导体集成电路的基板噪声分析装置公开(公告)号：US20050005254A1
公开(公告)日：2005-01-06
申请号：US10863327
申请日：2004-06-09
CPC分类号： G06F17/5036
摘要： In substrate noise analysis for a semiconductor integrated circuit, it takes long to calculate the amount of current input to the substrate and substrate potential fluctuations in an analog circuit to which the current is propagated in combination with impedance/power supply resistance of the substrate including a large scale RC circuit network. The amount of calculation is reduced in calculating current passed to power supply/ground by adding triangles having areas corresponding to power consumption separately for rising/falling in logical changes in gate level simulation. The amount of calculation is reduced by summing current, interface capacitance, interface resistance, power supply resistance, ground resistance, power supply voltage fluctuations, and ground voltage fluctuations on a basis of block, instance or simultaneous operation. Since the calculation amount is reduced, it takes a shorter period to apply substrate noise analysis. In addition, the elements for calculation are also reduced, and therefore substrate noise analysis can be applied to a large scale semiconductor integrated circuit.
摘要翻译： 在半导体集成电路的衬底噪声分析中，计算输入到衬底的电流量和电流传播到的模拟电路中的衬底电位波动与包括a的衬底的阻抗/电源电阻的组合需要很长时间 大型RC电路网络。 在计算通过电源/地电流的电流时，通过增加具有分别对应于功耗的区域的三角形来降低门级电平仿真中的逻辑变化中的上升/下降的计算量。 通过在块，实例或同时操作的基础上求和电流，接口电容，接口电阻，电源电阻，接地电阻，电源电压波动和接地电压波动来减少计算量。 由于计算量减少，所以需要较短的时间来应用衬底噪声分析。 此外，用于计算的元件也减少，因此衬底噪声分析可以应用于大规模半导体集成电路。
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6.发明授权公开(公告)号：US06782347B2
公开(公告)日：2004-08-24
申请号：US09993965
申请日：2001-11-27
IPC分类号： G06F308
CPC分类号： G06F17/5036 , Y02T10/82
摘要： A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.
摘要翻译： 一种用于优化电磁干扰（EMI）的方法，包括：EMI分析步骤，通过执行仿真分析LSI的电磁干扰量; 在所述EMI分析步骤中选择具有大量噪声的实例的步骤; 以及调整所述实例的驱动能力以使其降低到在所选择的所述实例的信号定时中不发生延迟的程度的步骤。 为了优化分析的EMI，提取需要优化的部分，并且在必要的程度上对该部分实现增加去耦电容的面积增加的措施。 此外，通过改变块的纵横比，改变块位置或改变单元行，可以在最有效的插入位置容易地创建去耦电容。
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公开(公告)号：US06754598B2
公开(公告)日：2004-06-22
申请号：US10193734
申请日：2002-07-12
IPC分类号： G06F1900
CPC分类号： G01R31/002 , Y02T10/82
摘要： A method of analyzing an electromagnetic interference amount of an LSI includes an equivalent impedance information calculating step of calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and an electromagnetic interference noise calculating step of calculating an electromagnetic interference noise based on the equivalent impedance information.
摘要翻译： 分析LSI的电磁干扰量的方法包括：等效阻抗信息计算步骤，其基于LSI芯片的电路信息和LSI芯片的封装信息来计算和估计等效阻抗信息;以及电磁干扰噪声计算步骤，计算 基于等效阻抗信息的电磁干扰噪声。
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公开(公告)号：US06959250B1
公开(公告)日：2005-10-25
申请号：US09615938
申请日：2000-07-13
CPC分类号： G06F17/5036 , Y02T10/82
摘要： In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of “the Static timing analysis technique”. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.
摘要翻译： 与已知的动态门级仿真方法相反，根据本发明的分析电磁干扰（EMI分析方法）的方法能够通过使用信号传播来计算每个节点的信号传播来估计EMI噪声 概率技术，并通过使用“静态时序分析技术”来计算每个节点的变化时间。 简而言之，本发明的特征在于根据每个节点的触发概率与每个节点的延迟之间的关系来计算频率特性。
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公开(公告)号：US06876210B2
公开(公告)日：2005-04-05
申请号：US09993595
申请日：2001-11-27
CPC分类号： G06F17/5022 , G01R31/002
摘要： A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.
摘要翻译： 一种分析其中分析来自LSI的电磁干扰量的电磁干扰的方法，其中所述方法包括：等效电源电流信息计算步骤，从电路中计算流过电源电流的等效电源电流的信息， LSI芯片的信息; 考虑将用于向LSI芯片提供电流的电源的电源信息，半导体芯片的封装的封装信息以及用于测量半导体芯片的特性的测量系统的测量系统信息中的至少一个的估计步骤 作为分析控制信息，并且将分析控制信息反映在电路信息中的总信息估计为等效电路; 以及总信息分析步骤，根据在估计步骤中估计的总信息进行分析。
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10.发明授权Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method 失效电磁干扰分析方法及装置及半导体器件制造方法采用该方法公开(公告)号：US06810340B2
公开(公告)日：2004-10-26
申请号：US10092737
申请日：2002-03-08
申请人： Kenji Shimazaki , Shouzou Hirano , Ritsuko Kurazono , Masanori Tsutsumi , Kaori Matsui , Hisato Yoshida , Hiroyuki Tsujikawa
发明人： Kenji Shimazaki , Shouzou Hirano , Ritsuko Kurazono , Masanori Tsutsumi , Kaori Matsui , Hisato Yoshida , Hiroyuki Tsujikawa
IPC分类号： G06F1900
CPC分类号： G01R31/2855
摘要： An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.
摘要翻译： 一种用于分析半导体集成电路的外部噪声的电磁干扰分析方法包括：阻抗提取步骤，提取目标半导体集成电路中的电力布线或半导体集成电路中的电力布线以及所述半导体集成电路的外部电力布线中的阻抗信息 半导体集成电路，从阻抗信息生成等效电路的等效电路生成步骤，以及分析步骤，从外部提供噪声波形，并分析噪声对半导体集成电路的影响。
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