公开(公告)号：US5781199A

公开(公告)日：1998-07-14

申请号：US749193

申请日：1996-11-14

申请人： Kazunori Oniki ,  Masahiro Shiraishi ,  Koji Ozawa ,  Keisuke Yamane ,  Shinji Kimura

发明人： Kazunori Oniki ,  Masahiro Shiraishi ,  Koji Ozawa ,  Keisuke Yamane ,  Shinji Kimura

IPC分类号： G06T11/00 ,  G06F15/80 ,  G06T1/00

CPC分类号： G06F15/8007

摘要： A parallel processing method for use with a graphics processor wherein graphics processing is performed by each of configured command processors efficiently in a distributed manner, with a host CPU remaining unaware of the number of command processors. Each command group of a variable length from a host CPU is distributed from an FIFO queue to a plurality of parallelly arranged command processors for parallel processing through any free one of input FIFO queues corresponding to the command processors. Upon command group distribution, an identical serial number is added as a command group serial number to the commands constituting the same command group. The results of processing of individual graphics commands by the command processors are collected via output FIFO queues, which also correspond to the processors, in the order of the command group serial numbers added to the commands before the processed results are graphically drawn.

摘要翻译： 一种与图形处理器一起使用的并行处理方法，其中图形处理由每个配置的命令处理器以分布式方式有效地执行，主机CPU仍然不知道命令处理器的数量。 来自主机CPU的可变长度的每个命令组从FIFO队列分配到多个并行布置的命令处理器，用于通过对应于命令处理器的任何空闲的一个输入FIFO队列进行并行处理。 在命令组分配时，将相同的序列号作为命令组序列号添加到构成同一命令组的命令。 命令处理器处理各个图形命令的结果通过输出FIFO队列收集，该队列也对应于处理器，按图形方式绘制处理结果之前的命令组序列号。

公开(公告)号：US5757364A

公开(公告)日：1998-05-26

申请号：US624826

申请日：1996-03-27

申请人： Koji Ozawa ,  Masahiro Shiraishi ,  Kazunori Oniki

发明人： Koji Ozawa ,  Masahiro Shiraishi ,  Kazunori Oniki

IPC分类号： G09G5/397 ,  G06T11/00 ,  G09G5/14 ,  G09G5/377 ,  G09G5/399 ,  G09G5/00 ,  G06F12/00

CPC分类号： G09G5/399 ,  G09G5/14 ,  G09G2340/12

摘要： The present invention relates to a graphic display apparatus for a multi-window graphic displaying system comprises a frame memory including double buffers for storing pixel data of display frames, first memorizing means for storing a successive frame number allocated to each pixel in each one of the display frames of which each set of pixel information is successively displayed and renewed, second memorizing means for storing window identifiers, each one of the identifiers being allocated in advance to each one of the multi-windows to be displayed, a table for storing the allocated frame numbers, information of designating one of buffers in the double-buffer and background color information, for each one of the multi-window, and means for comparing each one of the window identifiers and each one of the frame numbers read out from the first and second memorizing means, with each one of the window identifiers and each one of the frame numbers stored in the table, respectively, and for deciding pixel data to be displayed, based on results of the comparison, whereby it is not necessary to clear pixel data of the buffers for storing pixel data in each frame rendering, and the pixel data overwritten on the buffers need not to be cleared until the frame numbers overflow the first memorizing means.

摘要翻译： 本发明涉及一种用于多窗口图形显示系统的图形显示装置，包括：一个帧存储器，包括用于存储显示帧的像素数据的双重缓冲器;第一存储装置，用于存储分配给每个像素的每个像素的连续帧号 连续地显示和更新每组像素信息的显示帧，用于存储窗口标识符的第二存储装置，每个标识符被预先分配给要显示的多个窗口中的每一个，用于存储所分配的 帧数，对于多窗口中的每一个指定双缓冲器中的缓冲器之一的信息和背景颜色信息，以及用于比较每个窗口标识符和从第一个窗口读出的每个帧号的每个 以及第二存储装置，其中每个窗口标识符和每个帧编号分别存储在表中，并且对于d 基于比较结果来执行要显示的像素数据，由此不需要在每个帧渲染中清除用于存储像素数据的缓冲器的像素数据，并且不需要清除在缓冲器上重写的像素数据，直到 帧数溢出第一存储装置。

公开(公告)号：US07873871B2

公开(公告)日：2011-01-18

申请号：US11768241

申请日：2007-06-26

申请人： Masakazu Ishikawa ,  Akira Bandou ,  Masahiro Shiraishi ,  Masamitsu Kobayashi ,  Yasuyuki Furuta ,  Akihiro Onozuka ,  Shin Kokura ,  Eiji Kobayashi ,  Satoru Funaki ,  Takashi Umehara ,  Naoya Mashiko ,  Yuusuke Seki ,  Tatsuyuki Ootani

发明人： Masakazu Ishikawa ,  Akira Bandou ,  Masahiro Shiraishi ,  Masamitsu Kobayashi ,  Yasuyuki Furuta ,  Akihiro Onozuka ,  Shin Kokura ,  Eiji Kobayashi ,  Satoru Funaki ,  Takashi Umehara ,  Naoya Mashiko ,  Yuusuke Seki ,  Tatsuyuki Ootani

IPC分类号： G06F11/00

CPC分类号： G05B23/0229 ,  G05B23/0262

摘要： A programmable electronic controller in which one central arithmetic processing unit and a plurality of input devices and output devices are connected by means of a parallel bus, the controller being basically configured to activate a self-diagnostic function and a diagnostic test of the input devices and the output devices with an instruction from a microprocessor of the central arithmetic processing unit; and to judge the result with the microprocessor of the central arithmetic processing unit, by using the microprocessor installed in the central arithmetic processing unit also as a processor for tests (diagnostic tests) of the self-diagnostic function of the input devices and output devices and conducting tests of the self-diagnostic function of the plurality of input devices and output devices with the central arithmetic processing unit.

摘要翻译： 一种可编程电子控制器，其中一个中央算术处理单元和多个输入设备和输出设备通过并行总线连接，所述控制器基本上被配置为激活输入设备的自诊断功能和诊断测试， 所述输出装置具有来自所述中央算术处理单元的微处理器的指令; 并且通过使用安装在中央算术处理单元中的微处理器作为输入设备和输出设备的自诊断功能的测试（诊断测试）的处理器来判断结果与中央算术处理单元的微处理器，以及 利用中央算术处理单元对多个输入装置和输出装置进行自诊断功能的测试。

公开(公告)号：US07555627B2

公开(公告)日：2009-06-30

申请号：US11477468

申请日：2006-06-30

申请人： Naoya Mashiko ,  Takashi Umehara ,  Masamitsu Kobayashi ,  Hiromichi Endoh ,  Akihiro Onozuka ,  Akira Bando ,  Shin Kokura ,  Hisao Nagayama ,  Masakazu Ishikawa ,  Satoru Funaki ,  Masahiro Shiraishi

发明人： Naoya Mashiko ,  Takashi Umehara ,  Masamitsu Kobayashi ,  Hiromichi Endoh ,  Akihiro Onozuka ,  Akira Bando ,  Shin Kokura ,  Hisao Nagayama ,  Masakazu Ishikawa ,  Satoru Funaki ,  Masahiro Shiraishi

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/122 ,  Y02P90/14

摘要： Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.

摘要翻译： 通过提供输入输出控制装置，通过提供输入输出控制装置来防止输入输出装置由于处理器使用的输入输出值，以便以具有较高安全性要求的模式进行算术运算 第一存储区域，存储由处理器在具有相对较低安全性要求的模式下进行算术运算的输入输出值，并将其限制在第一存储区域中，并将复制从第一存储区域 区域，复制到第二存储区域，或者根据关于安全性要求的模式从第二存储区域进行复制。

公开(公告)号：US5346431A

公开(公告)日：1994-09-13

申请号：US22601

申请日：1993-02-17

申请人： Koshi Okuyama ,  Masahiro Shiraishi ,  Takashi Miyazaki

发明人： Koshi Okuyama ,  Masahiro Shiraishi ,  Takashi Miyazaki

IPC分类号： F16D3/84

CPC分类号： F16D3/848 ,  F16D2003/846

摘要： A sealing cover fitted on a coupling which connects an input shaft (1) and an output shaft (2) to each other for relative movement as in a U-joint including an outer member (3) having an outer spherical surface (3a) and connected to one of said shafts (2), comprises a first spherical shell (4) having an outer part made partly of a low flexibility material and having an inside part spherical surface slidably fitted on the outer spherical surface (3a), and a part spherical channel (7) open at the end of the shell near the other of the shafts (1), a second part spherical shell (8) slidably inserted at one end thereof into the channel (7) and fitted at the other end thereof on the shaft (1), a first sealing portion provided near one end of the first shell (4) in contact with the outer surface (3a) of the outer member (3), and a second sealing portion (10) provided near the other end of the first shell in contact with the outer part spherical surface (8c) of the second shell (8).

摘要翻译： 一种密封盖，其安装在将输入轴（1）和输出轴（2）彼此连接的联轴器上，以便在包括具有外球面（3a）的外部构件（3）的U形接头中相对移动，并且 连接到所述轴（2）中的一个，包括第一球壳（4），其具有部分由低柔性材料制成的外部部分，并且具有可滑动地装配在外球面（3a）上的内部球面， 球形通道（7）在壳体的另一端靠近壳体的端部开口，第二部分球形壳体（8）在其一端可滑动地插入通道（7）中，并在其另一端嵌合 所述轴（1），设置在与所述外部构件（3）的外表面（3a）接触的所述第一壳体（4）的一端附近的第一密封部分和设置在所述外部构件（3）附近的第二密封部分 第一壳体的端部与第二壳体（8）的外部球形表面（8c）接触。

公开(公告)号：US08493927B2

公开(公告)日：2013-07-23

申请号：US11769862

申请日：2007-06-28

申请人： Akira Bandou ,  Masamitsu Kobayashi ,  Masahiro Shiraishi ,  Akihiro Onozuka ,  Takashi Umehara ,  Shin Kokura ,  Eiji Kobayashi ,  Masakazu Ishikawa ,  Yasuyuki Furuta ,  Naoya Mashiko ,  Satoru Funaki ,  Yuusuke Seki ,  Tatsuyuki Ootani ,  Wataru Sasaki ,  Yusaku Otsuka ,  Akihiro Nakano ,  Shoichi Ozawa ,  Takenori Kasahara ,  Yu Iwasaki

发明人： Akira Bandou ,  Masamitsu Kobayashi ,  Masahiro Shiraishi ,  Akihiro Onozuka ,  Takashi Umehara ,  Shin Kokura ,  Eiji Kobayashi ,  Masakazu Ishikawa ,  Yasuyuki Furuta ,  Naoya Mashiko ,  Satoru Funaki ,  Yuusuke Seki ,  Tatsuyuki Ootani ,  Wataru Sasaki ,  Yusaku Otsuka ,  Akihiro Nakano ,  Shoichi Ozawa ,  Takenori Kasahara ,  Yu Iwasaki

IPC分类号： H04B7/212

CPC分类号： G05B9/02

摘要： In a control apparatus which transmits/receives data from a central processing unit via a serial transfer channel to a communication control unit, and groups/distributes data of input/output units from the communication control unit via a parallel transfer channel, the control apparatus initiates a diagnosing unit of the parallel transfer channel in response to an instruction issued from the central processing unit, and diagnosis the input/output units subsequent to the diagnosis of the transmission channel. Data input/output timing of the input/output unit is also instructed from the central processing unit, so that the central processing unit can suppress lowering of response speeds caused by the diagnoses, and can maintain the periodicity of the data input/output.

摘要翻译： 在通过串行传送信道向通信控制单元从中央处理单元发送/接收数据的控制装置中，通过并行传送信道对来自通信控制单元的输入/输出单元的数据进行分组/分配时，控制装置启动 响应于从中央处理单元发出的指令，并行传输信道的诊断单元，并且诊断传输信道诊断之后的输入/输出单元。 还从中央处理单元指示输入/输出单元的数据输入/输出定时，使得中央处理单元可以抑制由诊断引起的响应速度的降低，并且可以保持数据输入/输出的周期性。

公开(公告)号：US20120246399A1

公开(公告)日：2012-09-27

申请号：US13512958

申请日：2010-12-01

申请人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

发明人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (2), physical blocks are classified into three types: scratch blocks (22), data blocks (23), and erased blocks (24). Data writing from a host device (3) is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

摘要翻译： 公开了一种使用非易失性半导体存储器的存储装置，其实现了该装置的高性能和长寿命。 当管理非易失性半导体存储器（2）时，物理块被分为三种类型：暂存块（22），数据块（23）和擦除块（24）。 在暂存块上执行来自主机（3）的数据写入。 当暂存块内的空页数少于预定数量或不再存在时，该块被当作数据块处理，并且其中一个擦除块被新分配为暂存块。 如果擦除块不足，则从数据块中选择具有相对较少有效数据的块。 将块中包含的所有有效数据复制到暂存块后，块被擦除，从而获取被擦除的块。

公开(公告)号：US20070006025A1

公开(公告)日：2007-01-04

申请号：US11477440

申请日：2006-06-30

申请人： Akihiro Onozuka ,  Masakazu Ishikawa ,  Masamitsu Kobayashi ,  Takashi Umehara ,  Shin Kokura ,  Hiromichi Endoh ,  Satoru Funaki ,  Hisao Nagayama ,  Masahiro Shiraishi ,  Akira Bando ,  Eiji Kobayashi ,  Yasuyuki Furuta ,  Naoya Mashiko

发明人： Akihiro Onozuka ,  Masakazu Ishikawa ,  Masamitsu Kobayashi ,  Takashi Umehara ,  Shin Kokura ,  Hiromichi Endoh ,  Satoru Funaki ,  Hisao Nagayama ,  Masahiro Shiraishi ,  Akira Bando ,  Eiji Kobayashi ,  Yasuyuki Furuta ,  Naoya Mashiko

IPC分类号： G06F11/00

CPC分类号： H04L1/0046

摘要： The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.

摘要翻译： 该系统在发送装置中具有生成包括数据的发送数据的发生器，从数据生成的数据错误检测码和表示可靠度的安全标志，以及发送数据; 在接收装置中具有从接收到的帧中提取发送数据，安全标志和数据错误检测码的多个组件，并且检测数据错误，比较多个接收帧的匹配的比较器， 以及从帧错误检测结果，安全标志，数据错误检测结果和匹配比较结果中选择一个接收帧的选择器; 并通过与利用安全标志设定的可靠度相对应的检测来确定发送数据的有效性。

公开(公告)号：US08949515B2

公开(公告)日：2015-02-03

申请号：US13512958

申请日：2010-12-01

申请人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

发明人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (2), physical blocks are classified into three types: scratch blocks (22), data blocks (23), and erased blocks (24). Data writing from a host device (3) is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

摘要翻译： 公开了一种使用非易失性半导体存储器的存储装置，其实现了该装置的高性能和长寿命。 当管理非易失性半导体存储器（2）时，物理块被分为三种类型：暂存块（22），数据块（23）和擦除块（24）。 在暂存块上执行来自主机（3）的数据写入。 当暂存块内的空页数少于预定数量或不再存在时，该块被当作数据块处理，并且其中一个擦除块被新分配为暂存块。 如果擦除块不足，则从数据块中选择具有相对较少有效数据的块。 将块中包含的所有有效数据复制到暂存块后，块被擦除，从而获取被擦除的块。

公开(公告)号：US08161362B2

公开(公告)日：2012-04-17

申请号：US11447724

申请日：2006-06-07

申请人： Akira Bando ,  Shin Kokura ,  Takashi Umehara ,  Masamitsu Kobayashi ,  Hisao Nagayama ,  Naoya Mashiko ,  Masakazu Ishikawa ,  Masahiro Shiraishi ,  Akihiro Onozuka ,  Hiromichi Endoh ,  Tsutomu Yamada ,  Satoru Funaki

发明人： Akira Bando ,  Shin Kokura ,  Takashi Umehara ,  Masamitsu Kobayashi ,  Hisao Nagayama ,  Naoya Mashiko ,  Masakazu Ishikawa ,  Masahiro Shiraishi ,  Akihiro Onozuka ,  Hiromichi Endoh ,  Tsutomu Yamada ,  Satoru Funaki

IPC分类号： G06F11/00 ,  G06F7/02

CPC分类号： G06F9/3851 ,  G06F9/30189 ,  G06F9/3885 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1695 ,  G06F2201/845

摘要： Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.

摘要翻译： 当处理器对公共对象的数据进行兼容计算时，接收到处理的结果。 响应于来自任一个处理器的启动信号，生成计算命令信号并将其馈送到处理器，使得处理器可以用不同的操作定时进行计算。 然后，将处理器进行的计算的结果相互比较。 因此，可以通过使用处理器的上述结构来实现同时具有小尺寸，高性能和安全性的装置。