公开(公告)号：US06369617B1

公开(公告)日：2002-04-09

申请号：US09437268

申请日：1999-11-10

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： G11C800

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数 用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为 减少 通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加 的周期被启用。

公开(公告)号：US06677782B2

公开(公告)日：2004-01-13

申请号：US09840190

申请日：2001-04-24

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： H03K19096

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

摘要翻译： 为了加快解码电路的运行，解码电路的功耗降低，周期增加，解码电路中的缓冲器，预解码器，主译码器等电路由半导体逻辑电路构成， 用于在输出节点下拉的晶体管的列较小，即使输入数量多，并且获得具有大致相同延迟时间的真实和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为 根据本发明，可以加速解码器电路的操作，可以降低功耗，可以增加周期，并且在半导体存储器中，例如，减少访问时间和功耗以及增加 的周期被启用。

公开(公告)号：US06998878B2

公开(公告)日：2006-02-14

申请号：US10754596

申请日：2004-01-12

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： H03K19/20

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中， 在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是 减少 利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期 增加。

公开(公告)号：US06807115B2

公开(公告)日：2004-10-19

申请号：US10360867

申请日：2003-02-10

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

IPC分类号： G11C700

CPC分类号： G01R31/31701

摘要： In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

摘要翻译： 在每个周期执行预充电和评估操作的动态型半导体集成电路中，可以在评估期间进行IDDQ测试和光检测测试，以便于诊断和故障分析，从而提高测试精度。 动态型半导体集成电路在正常操作模式或测试模式下工作，其中其间的开关由模式选择信号触发。 在正常工作模式中，内部激活信号的脉冲宽度被控制为恒定的，即，以操作周期时间长度不变。 在测试模式中，内部激活信号的脉冲宽度被控制以根据操作周期时间长度而变化。

公开(公告)号：US06617610B2

公开(公告)日：2003-09-09

申请号：US10013474

申请日：2001-12-13

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Keiichi Higeta

IPC分类号： H01L2358

CPC分类号： G01R31/31701

摘要： In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

公开(公告)号：US6075729A

公开(公告)日：2000-06-13

申请号：US145161

申请日：1998-09-01

申请人： Kenichi Ohhata ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Keiichi Higeta

发明人： Kenichi Ohhata ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Keiichi Higeta

IPC分类号： G11C7/12 ,  G11C11/412 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C7/12 ,  G11C2207/12

摘要： A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.

摘要翻译： 半导体存储器具有多个字线，多个位线对和形成在字线和位线对之间的交点处的多个存储单元。 字解码器在接收到地址信号时产生字线选择信号，并且位解码器在接收到地址信号时产生位线选择信号。 位线负载电路从可应用的存储单元接收信号电流，感测电路检测来自位线负载电路的输出信号，位线下拉电路和位线恢复电路在写入时驱动可应用的位线 数据到所讨论的存储单元。 位线负载电路和位线恢复电路包括其漏极连接到位线并且其栅极被馈送控制信号的pMOS晶体管，以及其阳极连接到第一电源并且其阴极连接到源极的二极管 的pMOS晶体管，pMOS晶体管和二极管被提供给每个位线对。 在写周期期间位线被位线下拉电路驱动为低电平时，禁止pMOS晶体管导通，并允许其在包括读周期的其他周期期间导通。 这种结构缩短了恢复时间，实现了一个缩短周期时间的高速SRAM。

公开(公告)号：US06438050B1

公开(公告)日：2002-08-20

申请号：US10038914

申请日：2002-01-08

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Fumihiko Arakawa

IPC分类号： G11C700

CPC分类号： H03K3/356139

摘要： A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

摘要翻译： 一种用于通过信号线在电路单元之间传输数据信号的传输电路。 发送数据信号，用于在预充电期间将信号线预充电到高电位，并根据在评估期间传输的数据将其放电到低电位，或保持信号线原样。 锁存型源耦合逻辑被配置为使得用作下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位。 第二节点在评估期间根据第一节点的电位放电，第一节点根据信号线上的电位放电。 因此，可以加快由驱动电路对信号线进行放电的动作。

公开(公告)号：US06229745B1

公开(公告)日：2001-05-08

申请号：US09558375

申请日：2000-04-26

申请人： Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki

发明人： Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Fumihiko Arakawa ,  Takeshi Kusunoki

IPC分类号： G11C702

CPC分类号： G11C7/06

摘要： A semiconductor memory in accordance with the present invention includes a sense amplifier composed of a plurality of MOS transistors. When the sense amplifier is on standby, a first control circuit brings an input signal of the sense amplifier to zero. A second control circuit uses voltages developed because of an offset voltage occurring in the sense amplifier to feed back the potentials in the wells of the MOS transistors so that the offset voltage will be nullified. When the offset voltage occurring in the sense amplifier is nullified, a delay time required by the sense amplifier is shortened. This results in the high-speed semiconductor memory.

摘要翻译： 根据本发明的半导体存储器包括由多个MOS晶体管组成的读出放大器。 当读出放大器处于待机状态时，第一个控制电路使读出放大器的输入信号为零。 第二控制电路使用由于读出放大器中发生的偏移电压而产生的电压反馈MOS晶体管的阱中的电位，使得偏移电压将被无效。 当读出放大器中发生的失调电压无效时，读出放大器所需的延迟时间缩短。 这导致高速半导体存储器。

公开(公告)号：US06356493B1

公开(公告)日：2002-03-12

申请号：US09636737

申请日：2000-08-11

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Fumihiko Arakawa

IPC分类号： G11C700

CPC分类号： H03K3/356139

摘要： A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic as configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

摘要翻译： 一种用于通过信号线在电路单元之间传输数据信号的传输电路。 发送数据信号，用于在预充电期间将信号线预充电到高电位，并根据在评估期间传输的数据将其放电到低电位，或保持信号线原样。 锁存型源耦合逻辑被配置为使得用作下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位。 第二节点在评估期间根据第一节点的电位放电，第一节点根据信号线上的电位放电。 因此，可以加快由驱动电路对信号线进行放电的动作。

公开(公告)号：US06333881B1

公开(公告)日：2001-12-25

申请号：US09604735

申请日：2000-06-28

申请人： Takeshi Kusunoki ,  Fumihiko Arakawa ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki

发明人： Takeshi Kusunoki ,  Fumihiko Arakawa ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki

IPC分类号： G11C700

CPC分类号： G11C11/419 ,  G11C7/12

摘要： One of the factors determining cycle time of an SRAM is recovery time of a bit line after writing. When the size of a precharge PMOS transistor is increased to shorten the recovery time, delay time which is caused by making the precharge PMOS transistors non-conductive at the time of read operation, that is, access time increases. To avoid this, a semiconductor memory is provided with a second precharge circuit in addition to the conventional bit line precharge circuit. The second precharge circuit operates upon detection of completion of writing and stops operation when it detects that the bit line is precharged to a high potential. Consequently, the recovery time after write operation is shortened and the cycle time is reduced without increasing the access time.

摘要翻译： 确定SRAM周期时间的因素之一是写入后的位线的恢复时间。 当增加预充电PMOS晶体管的尺寸以缩短恢复时间时，由于在读取操作时使预充电PMOS晶体管不导通而导致的延迟时间，即访问时间增加。 为了避免这种情况，除了常规位线预充电电路之外，半导体存储器还设置有第二预充电电路。 第二预充电电路在检测到写入完成时工作，并且当其检测到位线被预充电到高电位时停止操作。 因此，在不增加访问时间的情况下，缩短写入操作之后的恢复时间并缩短周期时间。