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    SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开
    具有开放式线型存储器单元阵列的半导体存储器件及其控制方法

    公开(公告)号：US20110176379A1

    公开(公告)日：2011-07-21

    申请号：US13008408

    申请日：2011-01-18

    申请人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

    发明人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

    IPC分类号： G11C7/06

    CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

    摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.

    摘要翻译： 半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。 写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位 在第二位线的数据写入时的第二本地数据线。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08102695B2

    公开(公告)日：2012-01-24

    申请号：US12430067

    申请日：2009-04-25

    申请人： Kazuo Ono ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo Ono ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C7/18 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.

    摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关来并行提供两个电流路径。

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20110044092A1

    公开(公告)日：2011-02-24

    申请号：US12916499

    申请日：2010-10-30

    申请人： KAZUO ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： KAZUO ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C13/0011 ,  G11C13/0069 ,  G11C16/3468 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2213/52 ,  G11C2213/79

    摘要： A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.

    摘要翻译： 电阻变化存储器减少了编程之后的电阻值的不均匀性，使得可以以高速度对存储器单元执行重写操作。 参考电阻与电阻变化存储单元串联连接，传感器放大器检测存储单元和参考电阻之间的中间节点处的电位是否超过给定阈值电压，以便基于 检测结果。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20120092921A1

    公开(公告)日：2012-04-19

    申请号：US13330362

    申请日：2011-12-19

    申请人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C7/18 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.

    摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关来并行提供两个电流路径。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07835171B2

    公开(公告)日：2010-11-16

    申请号：US12172198

    申请日：2008-07-11

    申请人： Kazuo Ono ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo Ono ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C13/0011 ,  G11C13/0069 ,  G11C16/3468 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2213/52 ,  G11C2213/79

    摘要： A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.

    摘要翻译： 电阻变化存储器减少了编程之后的电阻值的不均匀性，使得可以以高速度对存储器单元执行重写操作。 参考电阻与电阻变化存储单元串联连接，传感器放大器检测存储单元和参考电阻之间的中间节点处的电位是否超过给定阈值电压，以便基于 检测结果。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090273961A1

    公开(公告)日：2009-11-05

    申请号：US12430067

    申请日：2009-04-25

    申请人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C5/02 ,  G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0023 ,  G11C7/18 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.

    摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关并联提供两个电流路径。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20120249180A1

    公开(公告)日：2012-10-04

    申请号：US13429056

    申请日：2012-03-23

    申请人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

    发明人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/35613

    摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

    摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。

    SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET 有权
    具有放大偏差的感测放大器电路的半导体存储器件

    公开(公告)号：US20110079858A1

    公开(公告)日：2011-04-07

    申请号：US12967728

    申请日：2010-12-14

    申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

    发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

    IPC分类号： H01L27/108

    CPC分类号： G11C11/4091 ,  H01L27/10897

    摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

    摘要翻译： 具有高集成度，低功耗和高操作速度的半导体存储器件。 存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。 构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。 具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。 数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

    Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages
    10.
    发明授权
    Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages 有权
    半导体存储器件包括具有P型读出放大器和具有不同阈值电压的N型读出放大器的读出放大器

    公开(公告)号：US07843751B2

    公开(公告)日：2010-11-30

    申请号：US12352347

    申请日：2009-01-12

    申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

    发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

    IPC分类号： G11C7/02

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

    摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

    摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。