公开(公告)号：US06534365B2

公开(公告)日：2003-03-18

申请号：US09726910

申请日：2000-11-29

Applicant: Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

Inventor： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

Abstract translation: 使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。 此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

公开(公告)号：US06211018B1

公开(公告)日：2001-04-03

申请号：US09475281

申请日：1999-12-30

Applicant: Kee Soo Nam ,  Sang Gi Kim ,  Tae Moon Roh ,  Jin Gun Koo

Inventor： Kee Soo Nam ,  Sang Gi Kim ,  Tae Moon Roh ,  Jin Gun Koo

IPC: H01L21336

CPC classification number: H01L29/66727 ,  H01L29/66348

Abstract: A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.

Abstract translation: 公开了半导体技术。 特别地，公开了一种用于锂离子二次电池保护电路，DC-DC转换器和电动机的低压大电流功率器件。 此外，公开了一种制造高密度沟槽栅型功率器件的方法。 也就是说，在本发明中，沟槽栅极掩模用于形成阱和/或源，为此，引入了侧壁间隔物。 以这种方式，通过使用沟槽栅极掩模来定义阱和/或源，因此与分开使用阱掩模和源掩模的常规工艺不同，跳过1或2个屏蔽处理。 掩蔽过程的使用减少会降低掩模对准误差，因此可以实现高密度。 因此，作为功率器件的重要因素的导通电阻可以降低。

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

Applicant: Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

Inventor： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC: H03L500

CPC classification number: H03K19/0016

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

Abstract translation: 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US06855581B2

公开(公告)日：2005-02-15

申请号：US10153975

申请日：2002-05-23

Applicant: Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

Inventor： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

IPC: H01L21/76 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

Abstract translation: 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

公开(公告)号：US06759714B2

公开(公告)日：2004-07-06

申请号：US10322232

申请日：2002-12-17

Applicant: Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

Inventor： Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

IPC: H01L2972

CPC classification number: H01L21/76289 ,  H01L21/84 ,  H01L23/367 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract translation: 提供半导体制造技术; 更具体地说，涉及具有使用绝缘体上硅（SOI）衬底的散热结构的半导体器件，以及制造半导体器件的方法。 本研究的装置和方法提供了具有高散热结构和高放热结构的半导体器件及其制造方法。 在研究中，通过在绝缘体上硅（SOI）衬底上形成集成电路，快速地通过隧道区域在衬底外部释放集成电路中产生的热和高频噪声，除去埋入 集成电路下的绝缘层形成隧道区。 当在隧道区域的上部和下部的表面上形成不均匀时，或者当具有优良导热性的空气或其它气体流入隧道区域时，可以进一步提高散热效率。

公开(公告)号：US09275304B2

公开(公告)日：2016-03-01

申请号：US13494906

申请日：2012-06-12

Applicant: Sanghun Yoon ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh

Inventor： Sanghun Yoon ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh

IPC: G06K9/62 ,  G06N99/00

CPC classification number: G06K9/6228 ,  G06K9/6269 ,  G06N99/005

Abstract: Disclosed is a feature vector classification device which includes an initial condition setting unit; a variable calculating unit configured to receive a training vector and to calculate an error and a weight according to setting of the initial condition setting unit; a loop deciding unit configured to determine whether re-calculation is required, based on a comparison result between the calculated error and an error threshold; and a hyperplane generating unit configured to generate a hyperplane when an end signal is received from the loop deciding unit.

Abstract translation: 公开了一种特征矢量分类装置，其包括初始状态设定单元， 可变计算单元，被配置为接收训练向量，并且根据初始条件设置单元的设置来计算误差和权重; 基于计算出的误差和误差阈值之间的比较结果，确定是否需要重新计算的循环判定单元; 以及超平面生成单元，被配置为当从所述循环判定单元接收到结束信号时，生成超平面。

公开(公告)号：US08150903B2

公开(公告)日：2012-04-03

申请号：US12136107

申请日：2008-06-10

Applicant: Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

Inventor： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

IPC: G06F7/57

CPC classification number: G06F7/57 ,  G06F7/5324 ,  G06F7/5338

Abstract: Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

Abstract translation: 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

公开(公告)号：US20120076408A1

公开(公告)日：2012-03-29

申请号：US12949438

申请日：2010-11-18

Applicant: Jung Hee SUK ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Jeong Hwan Lee ,  Jae Chang Shim ,  Mi Soon Choi ,  Wook Jin Chung ,  Yeung Hak LEE ,  Tae Moon Roh

Inventor： Jung Hee SUK ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Jeong Hwan Lee ,  Jae Chang Shim ,  Mi Soon Choi ,  Wook Jin Chung ,  Yeung Hak LEE ,  Tae Moon Roh

IPC: G06K9/34

CPC classification number: G06K9/3241 ,  G06K9/4642 ,  G06K9/6256

Abstract: Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data.

Abstract translation: 提供了用于检测对象的系统和方法。 该方法包括选择宏数据扫描模式，其中存在少量分割区域或微观扫描模式，其中根据包括要检测的对象的背景的复杂度存在大量分割区域，划分输入图像 根据所选择的扫描模式进入一个或多个区域，在分割区域中合并具有相似特征的相邻区域，通过从分割或合并区域排除具有高可能性的待检测对象不存在的区域来提取搜索区域 提取包括用于检测搜索区域中的对象的特征向量的特征数据，以及使用所提取的特征数据来检测搜索区域中的对象。

公开(公告)号：US20110153878A1

公开(公告)日：2011-06-23

申请号：US12882141

申请日：2010-09-14

Applicant: Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

Inventor： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

Abstract translation: 提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。 存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道 控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

公开(公告)号：US07958179B2

公开(公告)日：2011-06-07

申请号：US11978878

申请日：2007-10-30

Applicant: Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

Inventor： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

IPC: G06F7/38

CPC classification number: G06F7/57

Abstract: Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

Abstract translation: 提供了可重构处理器的算术方法和装置。 算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。