公开(公告)号：US06211018B1

公开(公告)日：2001-04-03

申请号：US09475281

申请日：1999-12-30

Applicant: Kee Soo Nam ,  Sang Gi Kim ,  Tae Moon Roh ,  Jin Gun Koo

Inventor： Kee Soo Nam ,  Sang Gi Kim ,  Tae Moon Roh ,  Jin Gun Koo

IPC: H01L21336

CPC classification number: H01L29/66727 ,  H01L29/66348

Abstract: A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.

Abstract translation: 公开了半导体技术。 特别地，公开了一种用于锂离子二次电池保护电路，DC-DC转换器和电动机的低压大电流功率器件。 此外，公开了一种制造高密度沟槽栅型功率器件的方法。 也就是说，在本发明中，沟槽栅极掩模用于形成阱和/或源，为此，引入了侧壁间隔物。 以这种方式，通过使用沟槽栅极掩模来定义阱和/或源，因此与分开使用阱掩模和源掩模的常规工艺不同，跳过1或2个屏蔽处理。 掩蔽过程的使用减少会降低掩模对准误差，因此可以实现高密度。 因此，作为功率器件的重要因素的导通电阻可以降低。

公开(公告)号：US06534365B2

公开(公告)日：2003-03-18

申请号：US09726910

申请日：2000-11-29

Applicant: Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

Inventor： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

Abstract translation: 使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。 此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

公开(公告)号：US06855581B2

公开(公告)日：2005-02-15

申请号：US10153975

申请日：2002-05-23

Applicant: Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

Inventor： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

IPC: H01L21/76 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

Abstract translation: 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

Applicant: Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

Inventor： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC: H03L500

CPC classification number: H03K19/0016

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

Abstract translation: 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US06759714B2

公开(公告)日：2004-07-06

申请号：US10322232

申请日：2002-12-17

Applicant: Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

Inventor： Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

IPC: H01L2972

CPC classification number: H01L21/76289 ,  H01L21/84 ,  H01L23/367 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract translation: 提供半导体制造技术; 更具体地说，涉及具有使用绝缘体上硅（SOI）衬底的散热结构的半导体器件，以及制造半导体器件的方法。 本研究的装置和方法提供了具有高散热结构和高放热结构的半导体器件及其制造方法。 在研究中，通过在绝缘体上硅（SOI）衬底上形成集成电路，快速地通过隧道区域在衬底外部释放集成电路中产生的热和高频噪声，除去埋入 集成电路下的绝缘层形成隧道区。 当在隧道区域的上部和下部的表面上形成不均匀时，或者当具有优良导热性的空气或其它气体流入隧道区域时，可以进一步提高散热效率。

公开(公告)号：US07190432B2

公开(公告)日：2007-03-13

申请号：US11249783

申请日：2005-10-13

Applicant: Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

Inventor： Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

IPC: G03B27/32 ,  G03B27/42 ,  G03B27/70 ,  G03B27/54

CPC classification number: G03F7/70425

Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Abstract translation: 提供了一种在半导体器件制造工艺中使用的晶片曝光装置，该曝光装置包括：用于反射从光源提供的光的反射镜; 用于改变从反射镜提供的光的路径的光路改变器; 首先将镜子安装在光路改换器的两侧，以改变光线的路径; 第二个镜子安装在材料的两侧以改变光线的路径; 和第三反射镜，其安装在掩模的两侧，以将由第一反射镜反射的光进入掩模，并将通过掩模的光进入第二反射镜，由此可以连续地将一个表面，两个表面或一个 在晶片一次对准的状态下晶片的比表面。

公开(公告)号：US20060079030A1

公开(公告)日：2006-04-13

申请号：US11179983

申请日：2005-07-12

Applicant: Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

Inventor： Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

IPC: H01L21/8232 ,  H01L21/338

CPC classification number: H01L21/28587

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

公开(公告)号：US07170044B2

公开(公告)日：2007-01-30

申请号：US10913398

申请日：2004-08-09

Applicant: Kun Sik Pakr ,  Seong Wook Yoo ,  Jong Moon Park ,  Yong Sun Yoon ,  Sang Gi Kim ,  Bo Woo Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo

Inventor： Kun Sik Pakr ,  Seong Wook Yoo ,  Jong Moon Park ,  Yong Sun Yoon ,  Sang Gi Kim ,  Bo Woo Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo

IPC: H01J40/14

CPC classification number: H01L31/02161 ,  H01L31/02019 ,  H01L31/022408

Abstract: Provided is a photodetector in which a transparent nonconductive material having an interface charge and a trapped charge is deposited on a semiconductor surface so as to form a depletion region on the surface of the semiconductor, and the depletion region is employed as an optical detecting region, thereby not only improving detection with respect to light having a wavelength of ultraviolet and blue ranges but also filtering light having a wavelength of visible and infrared ranges, and in which a fabricating process thereof is compatible with a universal silicon CMOS process.

Abstract translation: 提供了一种光电检测器，其中具有界面电荷和俘获电荷的透明非导电材料沉积在半导体表面上，以在半导体的表面上形成耗尽区，并且耗尽区被用作光学检测区域， 从而不仅能够提高对具有紫外线和蓝色范围的波长的光的检测，而且可以改善具有可见光和红外范围的波长的滤光，并且其制造方法与通用硅CMOS工艺相兼容。

公开(公告)号：US20060109444A1

公开(公告)日：2006-05-25

申请号：US11249783

申请日：2005-10-13

Applicant: Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

Inventor： Sang Gi Kim ,  Ju Wook Lee ,  Jong Moon Park ,  Seong Wook Yoo ,  Kun Sik Park ,  Yong Sun Yoon ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Boo Woo Kim

IPC: G03B27/54

CPC classification number: G03F7/70425

Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Abstract translation: 提供了一种在半导体器件制造工艺中使用的晶片曝光装置，该曝光装置包括：用于反射从光源提供的光的反射镜; 用于改变从反射镜提供的光的路径的光路改变器; 首先将镜子安装在光路改换器的两侧，以改变光线的路径; 第二个镜子安装在材料的两侧以改变光线的路径; 和第三反射镜，其安装在掩模的两侧，以将由第一反射镜反射的光进入掩模，并将通过掩模的光进入第二反射镜，由此可以连续地将一个表面，两个表面或一个 在晶片一次对准的状态下晶片的比表面。

公开(公告)号：US08629020B2

公开(公告)日：2014-01-14

申请号：US13228479

申请日：2011-09-09

Applicant: Sang Gi Kim ,  Jin-Gun Koo ,  Seong Wook Yoo ,  Jong-Moon Park ,  Jin Ho Lee ,  Kyoung Il Na ,  Yil Suk Yang ,  Jongdae Kim

Inventor： Sang Gi Kim ,  Jin-Gun Koo ,  Seong Wook Yoo ,  Jong-Moon Park ,  Jin Ho Lee ,  Kyoung Il Na ,  Yil Suk Yang ,  Jongdae Kim

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。