公开(公告)号：US20070279112A1

公开(公告)日：2007-12-06

申请号：US10589428

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched to a logic “1” by start of one clock cycle of the internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting the duration time of the logic “1” of the first signal inputted by the variable delay addition circuit through the dummy delay until one clock cycle of the internal clock is completed and setting the initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 使用具有用于比较内部时钟和延迟时钟的相位的相位比较电路的DLL电路的半导体存储器和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括：用于输入第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的一个时钟周期的开始锁存到逻辑“1”，并通过第一信号的逻辑“1”的持续时间检测装置 通过可变延迟加法电路通过虚拟延迟输入，直到内部时钟的一个时钟周期完成，并根据持续时间设定可变延迟加法电路的延迟量的初始值。

公开(公告)号：US20070279113A1

公开(公告)日：2007-12-06

申请号：US10590225

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K5/1534 ,  H03L7/0818

摘要： A DLL circuit comprises a dummy delay corresponding to an internal clock delay from an external clock, a variable delay addition circuit having a coarse and fine delay circuits adjusting delay amount according to a delay amount adjustment signal, and a phase comparison circuit comparing phases of the internal clock and a delay clock input via the variable delay addition circuit and the dummy delay and outputting the delay amount adjustment signal to the variable delay addition circuit. At the start of burst, a first signal set at a logic “1” during 1 clock cycle of the internal clock is input to the variable delay addition circuit via the dummy delay, and duration time of the logic “1” of the first signal is detected until 1 clock cycle of the internal clock is completed and delay amount of the variable delay addition circuit is initialized by setting one of the coarse delay circuit based on the duration time.

摘要翻译： DLL电路包括对应于来自外部时钟的内部时钟延迟的虚拟延迟，具有根据延迟量调整信号调整延迟量的粗略和精细延迟电路的可变延迟加法电路，以及相位比较电路， 内部时钟和通过可变延迟加法电路输入的延迟时钟和虚拟延迟，并将延迟量调整信号输出到可变延迟加法电路。 在突发开始时，在内部时钟的1个时钟周期期间被设置为逻辑“1”的第一信号经由虚拟延迟被输入到可变延迟加法电路，并且第一信号的逻辑“1”的持续时间 被检测到内部时钟的1个时钟周期完成，并且通过基于持续时间设置粗略延迟电路之一来初始化可变延迟加法电路的延迟量。

公开(公告)号：US20100030943A1

公开(公告)日：2010-02-04

申请号：US10589375

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： G06F12/00

CPC分类号： G11C16/32 ,  G11C7/1027 ,  G11C7/1072

摘要： A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal.

摘要翻译： 具有与时钟信号同步的突发模式读取功能的半导体存储器包括由多个存储器单元组成的存储器阵列，用于将接收到的地址的上部组释放为存储器访问地址的同步读取控制电路和下部组 的接收地址作为与时钟信号同步的突发地址;读出放大器，用于释放由存储器地址选择的每个存储器单元的输出数据，解码器，用于解码突发地址;地址锁存器，用于锁存解码的 突发地址与时钟信号同步，用于保存输出数据并选择由地址锁存器的突发地址确定的输出数据中的相应一个的页选择器，以及用于与时钟信号同步地锁存输出数据的输出锁存器 。

公开(公告)号：US20070279111A1

公开(公告)日：2007-12-06

申请号：US10589403

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A DLL circuit having a phase comparison circuit for comparing phases of a reference clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched at a logic “1” by start of 1 clock cycle of an internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting duration time of the logic “1” of the first signal input by the variable delay addition circuit through the dummy delay until the end of the 1 clock cycle of the internal clock and setting an initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 具有用于比较参考时钟和延迟时钟的相位的相位比较电路的DLL电路和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括用于输入锁存在逻辑上的第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的1个时钟周期开始到可变延迟加法电路的“1”和用于检测由可变延迟输入的第一信号的逻辑“1”的持续时间的装置 通过虚拟延迟的加法电路，直到内部时钟的1个时钟周期结束，并且基于持续时间设置可变延迟加法电路的延迟量的初始值。

公开(公告)号：US06262910B1

公开(公告)日：2001-07-17

申请号：US09417274

申请日：1999-10-13

申请人： Hidekazu Takata ,  Kengo Maeda

发明人： Hidekazu Takata ,  Kengo Maeda

IPC分类号： G11C1112

CPC分类号： G11C11/22

摘要： A switching transistor is provided which applies predetermined voltage to a plurality of word lines based on a predetermined signal from a power on reset circuit, until predetermined potential becomes stable, when the predetermined potential is applied to the bit line or to the plate line, such as at the time of power on, to connect the bit line connected to each memory cell and the memory cell capacitor, as well as applies a control signal to the gate to thereby electrically connect the bit line and the plate line.

摘要翻译： 提供了一种开关晶体管，当预定电位施加到位线或板线时，基于来自上电复位电路的预定信号，将预定电压施加到多个字线，直到预定电位变稳定为止 在上电时，连接连接到每个存储单元的位线和存储单元电容器，以及向门施加控制信号从而电连接位线和板线。

公开(公告)号：US20090266111A1

公开(公告)日：2009-10-29

申请号：US12084857

申请日：2006-11-13

申请人： Yukihito Nagashima ,  Kengo Maeda

发明人： Yukihito Nagashima ,  Kengo Maeda

IPC分类号： C03B5/225

CPC分类号： C03B1/00 ,  C03C1/004 ,  C03C3/091

摘要： Provided is a method of producing a glass, including, in order to obtain an excellent refining effect: preparing a raw glass batch including: an antimony compound containing pentavalent antimony; and an oxidizing agent (a cerium oxide, a sulfate, a nitrate); and melting the raw glass batch. In preparing the raw glass batch, it is preferable that the antimony compound be premixed with the oxidizing agent. When the nitrate is used as the oxidizing agent, the raw glass batch is prepared so as to include the antimony compound in an amount of more than 0.5 parts by mass and at most 3 parts by mass, in terms of an amount of antimony pentoxide, per 100 parts by mass of a base glass composition expressed in terms of an amount of an oxide.

摘要翻译： 提供一种制造玻璃的方法，其包括为了获得优异的澄清效果：制备原料玻璃批料，其包括：含有五价锑的锑化合物; 和氧化剂（氧化铈，硫酸盐，硝酸盐）; 并熔化原料玻璃批次。 在制备原料玻璃批料时，优选将锑化合物与氧化剂预混合。 当硝酸盐用作氧化剂时，制备原料玻璃批料，以包含锑化合物的量超过0.5质量份，最多3质量份，以五氧化二锑的量计， 相对于以氧化物量表示的基础玻璃组合物100质量份。

公开(公告)号：US06529826B2

公开(公告)日：2003-03-04

申请号：US09995653

申请日：2001-11-29

申请人： Tomoyuki Kawai ,  Kengo Maeda

发明人： Tomoyuki Kawai ,  Kengo Maeda

IPC分类号： G01C2100

CPC分类号： G01C21/3629 ,  G01C21/3605 ,  G01C21/3679

摘要： A navigation apparatus for guiding a moving body from a current location to a destination using a communication base station includes a current location detection device for detecting a current location of the moving body and outputting current location information; a sending device for sending the current location information and destination information to the communication base station; a receiving device for receiving guiding information, which is required to guide the moving body from the current location to the destination and includes information representing a location of a guiding point and a navigation message corresponding to the guiding point, from the communication base station; a memory device for storing the guiding information; and a voice processing device for outputting the navigation message in voice format, based on the current location information and the information representing the location of the guiding point which is included in the guiding information.

公开(公告)号：US20140166135A1

公开(公告)日：2014-06-19

申请号：US14115282

申请日：2012-05-11

申请人： Koji Yamashita ,  Masayuki Komiyama ,  Kazushige Koiwai ,  Koji Ueda ,  Kengo Maeda

发明人： Koji Yamashita ,  Masayuki Komiyama ,  Kazushige Koiwai ,  Koji Ueda ,  Kengo Maeda

IPC分类号： E02F9/22 ,  E02F9/12

CPC分类号： E02F9/2296 ,  E02F9/123 ,  E02F9/2235 ,  E02F9/2285 ,  F15B9/03 ,  F15B9/14 ,  G05B11/14 ,  G05B2219/45012 ,  Y10T137/86027

摘要： A slewing-type working machine includes: a slewing motor which is a hydraulic motor for slewing; a variable-displacement hydraulic pump; a slewing operation device including an operation member; a control valve controlling the slewing motor based on an operation signal thereof; a pump regulator; a relief valve letting excess fluid to a tank; operation detectors detecting an operation direction and amount of the operation member; a motor rotational speed detector; and a controller controlling a discharge flow rate of the hydraulic pump. The controller obtains a deviation between a target rotational speed of the slewing motor obtained from a slewing operation amount and an actual rotational speed detected by the motor rotational speed detector, and controls the discharge flow rate to make the deviation closer to 0.

摘要翻译： 回转式加工机包括：回转马达，其是用于回转的液压马达; 可变排量液压泵; 包括操作构件的回转操作装置; 基于其操作信号控制所述回转马达的控制阀; 泵调节器; 一个安全阀，让多余的液体进入一个水箱; 操作检测器检测操作构件的操作方向和量; 电动机转速检测器; 以及控制液压泵的排出流量的控制器。 控制器获得从回转运算量获得的回转马达的目标转速与由马达转速检测器检测到的实际转速之间的偏差，并控制排出流量使偏差接近0。

公开(公告)号：US20110287568A1

公开(公告)日：2011-11-24

申请号：US13148278

申请日：2010-02-05

申请人： Yuji Suzuki ,  Akinori Izumi ,  Kengo Maeda

发明人： Yuji Suzuki ,  Akinori Izumi ,  Kengo Maeda

IPC分类号： H01L31/18

CPC分类号： H01L31/02008 ,  H01L31/022425 ,  Y02E10/50

摘要： A method of manufacturing a thin film solar cell includes a bonding step of bonding a bus bar on a back face electrode layer of a solar cell string including a transparent conductive film, a photoelectric conversion layer and the back face electrode layer formed on a light-transmitting insulating substrate. The bonding step includes a first step of bonding conductive tape on the bonding surface of the bus bar that is to be bonded to the back face electrode layer, and a second step of bonding the bus bar to which the conductive tape has been bonded to the back face electrode layer of the solar cell string.

摘要翻译： 制造薄膜太阳能电池的方法包括将汇流条接合在包括透明导电膜，光电转换层和形成在发光二极管上的背面电极层的太阳能电池串的背面电极层上的接合步骤， 传输绝缘基板。 接合步骤包括将导电带接合到要接合到背面电极层的母线的接合表面上的第一步骤，以及将导电带已经结合到母线上的第二步骤 太阳能电池串的背面电极层。

公开(公告)号：US06400602B2

公开(公告)日：2002-06-04

申请号：US09818194

申请日：2001-03-26

申请人： Hidekazu Takata ,  Kengo Maeda ,  Yasumichi Mori

发明人： Hidekazu Takata ,  Kengo Maeda ,  Yasumichi Mori

IPC分类号： G11C1606

CPC分类号： G11C29/76 ,  G11C29/88 ,  G11C29/883

摘要： A semiconductor memory device includes: a plurality of memory cell regions, each comprising at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section. At least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.

摘要翻译： 半导体存储器件包括：多个存储单元区域，每个存储单元区域包括至少一个存储单元; 接受外部写入的非易失性存储器部分; 以及取消选择装置，用于基于写入所述非易失性存储器部分的数据来指定所述多个存储器单元区域中的至少一个是不可访问的。 对于多个存储单元区域中的至少一个不被指定为不可访问的可访问存储单元区域执行至少一种操作类型。