公开(公告)号：US20100030943A1

公开(公告)日：2010-02-04

申请号：US10589375

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： G06F12/00

CPC分类号： G11C16/32 ,  G11C7/1027 ,  G11C7/1072

摘要： A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal.

摘要翻译： 具有与时钟信号同步的突发模式读取功能的半导体存储器包括由多个存储器单元组成的存储器阵列，用于将接收到的地址的上部组释放为存储器访问地址的同步读取控制电路和下部组 的接收地址作为与时钟信号同步的突发地址;读出放大器，用于释放由存储器地址选择的每个存储器单元的输出数据，解码器，用于解码突发地址;地址锁存器，用于锁存解码的 突发地址与时钟信号同步，用于保存输出数据并选择由地址锁存器的突发地址确定的输出数据中的相应一个的页选择器，以及用于与时钟信号同步地锁存输出数据的输出锁存器 。

公开(公告)号：US20070279111A1

公开(公告)日：2007-12-06

申请号：US10589403

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A DLL circuit having a phase comparison circuit for comparing phases of a reference clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched at a logic “1” by start of 1 clock cycle of an internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting duration time of the logic “1” of the first signal input by the variable delay addition circuit through the dummy delay until the end of the 1 clock cycle of the internal clock and setting an initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 具有用于比较参考时钟和延迟时钟的相位的相位比较电路的DLL电路和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括用于输入锁存在逻辑上的第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的1个时钟周期开始到可变延迟加法电路的“1”和用于检测由可变延迟输入的第一信号的逻辑“1”的持续时间的装置 通过虚拟延迟的加法电路，直到内部时钟的1个时钟周期结束，并且基于持续时间设置可变延迟加法电路的延迟量的初始值。

公开(公告)号：US20120246422A1

公开(公告)日：2012-09-27

申请号：US13492119

申请日：2012-06-08

申请人： Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

发明人： Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

IPC分类号： G06F12/00

CPC分类号： G11C16/06

摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

公开(公告)号：US08219744B2

公开(公告)日：2012-07-10

申请号：US13301969

申请日：2011-11-22

申请人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

发明人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

IPC分类号： G06F12/02

CPC分类号： G11C16/06

摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

公开(公告)号：US20120063229A1

公开(公告)日：2012-03-15

申请号：US13301969

申请日：2011-11-22

申请人： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

发明人： Takahiro SUZUKI ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

IPC分类号： G11C16/26

CPC分类号： G11C16/06

摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

公开(公告)号：US20080177928A1

公开(公告)日：2008-07-24

申请号：US12018493

申请日：2008-01-23

申请人： Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

发明人： Takahiro SUZUKI ,  Shinya FUJISAWA ,  Tokumasa HARA ,  Masuji NISHIYAMA

IPC分类号： G06F12/00

CPC分类号： G11C16/06

摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

公开(公告)号：US20070279112A1

公开(公告)日：2007-12-06

申请号：US10589428

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched to a logic “1” by start of one clock cycle of the internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting the duration time of the logic “1” of the first signal inputted by the variable delay addition circuit through the dummy delay until one clock cycle of the internal clock is completed and setting the initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 使用具有用于比较内部时钟和延迟时钟的相位的相位比较电路的DLL电路的半导体存储器和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括：用于输入第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的一个时钟周期的开始锁存到逻辑“1”，并通过第一信号的逻辑“1”的持续时间检测装置 通过可变延迟加法电路通过虚拟延迟输入，直到内部时钟的一个时钟周期完成，并根据持续时间设定可变延迟加法电路的延迟量的初始值。

公开(公告)号：US08082383B2

公开(公告)日：2011-12-20

申请号：US12018493

申请日：2008-01-23

申请人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

发明人： Takahiro Suzuki ,  Shinya Fujisawa ,  Tokumasa Hara ,  Masuji Nishiyama

IPC分类号： G06F13/00

CPC分类号： G11C16/06

摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

摘要翻译： 半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。 存储单元阵列包括非易失性存储单元。 电源电路包括第一寄存器并产生电压。 读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。 控制电路包括第三寄存器并控制电源电路和读出放大器的操作。 处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。 控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

公开(公告)号：US20070279113A1

公开(公告)日：2007-12-06

申请号：US10590225

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K5/1534 ,  H03L7/0818

摘要： A DLL circuit comprises a dummy delay corresponding to an internal clock delay from an external clock, a variable delay addition circuit having a coarse and fine delay circuits adjusting delay amount according to a delay amount adjustment signal, and a phase comparison circuit comparing phases of the internal clock and a delay clock input via the variable delay addition circuit and the dummy delay and outputting the delay amount adjustment signal to the variable delay addition circuit. At the start of burst, a first signal set at a logic “1” during 1 clock cycle of the internal clock is input to the variable delay addition circuit via the dummy delay, and duration time of the logic “1” of the first signal is detected until 1 clock cycle of the internal clock is completed and delay amount of the variable delay addition circuit is initialized by setting one of the coarse delay circuit based on the duration time.

摘要翻译： DLL电路包括对应于来自外部时钟的内部时钟延迟的虚拟延迟，具有根据延迟量调整信号调整延迟量的粗略和精细延迟电路的可变延迟加法电路，以及相位比较电路， 内部时钟和通过可变延迟加法电路输入的延迟时钟和虚拟延迟，并将延迟量调整信号输出到可变延迟加法电路。 在突发开始时，在内部时钟的1个时钟周期期间被设置为逻辑“1”的第一信号经由虚拟延迟被输入到可变延迟加法电路，并且第一信号的逻辑“1”的持续时间 被检测到内部时钟的1个时钟周期完成，并且通过基于持续时间设置粗略延迟电路之一来初始化可变延迟加法电路的延迟量。