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公开(公告)号：US20050083736A1
公开(公告)日：2005-04-21
申请号：US10961134
申请日：2004-10-12
申请人： Kenichi Fukui , Mitsuru Hiraki , Mitsuhiko Okutsu
发明人： Kenichi Fukui , Mitsuru Hiraki , Mitsuhiko Okutsu
摘要： In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage. The transistor of the first switch for clamping the voltage may be remarkably reduced in size in comparison with an output transistor of the output buffer. Accordingly, the area occupied by the chip is not enlarged.
摘要翻译： 考虑到在输入电源时控制过冲，而不增加安装在半导体集成电路上的电压产生电路中的芯片占用的面积，内部电压产生电路包括电压产生电路，用于从第一 从外部提供的电压，以及用于产生对应于第二电压的第三电压的输出缓冲器。 第三电压用作内部电路的工作电源。 此外，还提供了用于使得第二电压的输出节点能够导通到预定电位的第一开关和用于响应于第一电压的输入而使第一开关接通预定时段的控制电路。 输出缓冲器的输出端子不被钳位，而前一级的电压产生电路的输出被钳位到预定电压。 与输出缓冲器的输出晶体管相比，用于钳位电压的第一开关的晶体管的尺寸可以显着减小。 因此，芯片所占据的面积不会扩大。
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公开(公告)号：US07126872B2
公开(公告)日：2006-10-24
申请号：US10961134
申请日：2004-10-12
申请人： Kenichi Fukui , Mitsuru Hiraki , Mitsuhiko Okutsu
发明人： Kenichi Fukui , Mitsuru Hiraki , Mitsuhiko Okutsu
摘要： In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage. The transistor of the first switch for clamping the voltage may be remarkably reduced in size in comparison with an output transistor of the output buffer. Accordingly, the area occupied by the chip is not enlarged.
摘要翻译： 考虑到在输入电源时控制过冲，而不增加安装在半导体集成电路上的电压产生电路中的芯片占用的面积，内部电压产生电路包括电压产生电路，用于从第一 从外部提供的电压，以及用于产生对应于第二电压的第三电压的输出缓冲器。 第三电压用作内部电路的工作电源。 此外，还提供了用于使得第二电压的输出节点能够导通到预定电位的第一开关和用于响应于第一电压的输入而使第一开关接通预定时段的控制电路。 输出缓冲器的输出端子不被钳位，而前一级的电压产生电路的输出被钳位到预定电压。 与输出缓冲器的输出晶体管相比，用于钳位电压的第一开关的晶体管的尺寸可以显着减小。 因此，芯片所占据的面积不会扩大。
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公开(公告)号：US20090039846A1
公开(公告)日：2009-02-12
申请号：US12251519
申请日：2008-10-15
申请人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
发明人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
IPC分类号： G05F1/565
CPC分类号： H03K17/22 , H03K17/163
摘要： In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ΔV between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
摘要翻译： 为了高精度地设定在接通电源时在功率开关电路中流动的冲击电流的值，LSI的内部电路Int_Cir从输出晶体管MP1被提供内部源极电压Vint 的稳压器VReg的电源开关电路PSWC。 电源开关电路PSWC包括控制电路CNTRLR和启动电路STC。 在电源的“接通”之后的初始时段期间，启动电路STC控制输出晶体管MP1并降低初级冲击电流，使得输出晶体管MP1的输出电流Isup可以表示近似恒定的增量 随着时间的流逝。 由负载电容C的内部电流电压与由启动电路STC控制的输出电流Isup和来自调节器VReg的当前电压Vint之间的差值DeltaV设定在预定极限内，以减小二次冲击电流 。
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公开(公告)号：US20070145922A1
公开(公告)日：2007-06-28
申请号：US11606031
申请日：2006-11-30
申请人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
发明人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
IPC分类号： H02P3/00
CPC分类号： H03K17/22 , H03K17/163
摘要： In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ΔV between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
摘要翻译： 为了高精度地设置在接通电源时在功率开关电路中流动的冲击电流的值，LSI的内部电路Int_Cir从输出晶体管MP提供内部源极电压Vint 电源开关电路PSWC的调节器VReg中的1个。 电源开关电路PSWC包括控制电路CNTRLR和启动电路STC。 在电源的“接通”之后的初始阶段期间，启动电路STC控制输出晶体管MP1并减小初级冲击电流，使得输出晶体管MP 1的输出电流Isup可以表示大约 随着时间的推移不断增加。 由负载电容C的内部电流电压与由启动电路STC控制的输出电流Isup和来自调节器VReg的当前电压Vint之间的差值DeltaV设定在预定极限内，以减小二次冲击电流 。
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公开(公告)号：US07652863B2
公开(公告)日：2010-01-26
申请号：US12251519
申请日：2008-10-15
申请人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
发明人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
IPC分类号： H02H3/08
CPC分类号： H03K17/22 , H03K17/163
摘要： In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ΔV between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
摘要翻译： 为了高精度地设定在接通电源时在功率开关电路中流动的冲击电流的值，LSI的内部电路Int_Cir从输出晶体管MP1被提供内部源极电压Vint 的稳压器VReg的电源开关电路PSWC。 电源开关电路PSWC包括控制电路CNTRLR和启动电路STC。 在电源的“接通”之后的初始时段期间，启动电路STC控制输出晶体管MP1并降低初级冲击电流，使得输出晶体管MP1的输出电流Isup可以表示近似恒定的增量 随着时间的流逝。 由负载电容C的内部电流电压与由启动电路STC控制的输出电流Isup和来自调节器VReg的当前电压Vint之间的差值DeltaV设定在预定极限内，以减小二次冲击电流 。
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公开(公告)号：US07450361B2
公开(公告)日：2008-11-11
申请号：US11606031
申请日：2006-11-30
申请人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
发明人： Takayasu Ito , Mitsuru Hiraki , Satoshi Baba , Kenichi Fukui
IPC分类号： H02H3/08
CPC分类号： H03K17/22 , H03K17/163
摘要： In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ΔV between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
摘要翻译： 为了高精度地设置在接通电源时在功率开关电路中流动的冲击电流的值，LSI的内部电路Int_Cir从输出晶体管MP提供内部源极电压Vint 电源开关电路PSWC的调节器VReg中的1个。 电源开关电路PSWC包括控制电路CNTRLR和启动电路STC。 在电源的“接通”之后的初始阶段期间，启动电路STC控制输出晶体管MP1并减小初级冲击电流，使得输出晶体管MP 1的输出电流Isup可以表示大约 随着时间的推移不断增加。 由负载电容C的内部电流电压与由启动电路STC控制的输出电流Isup和来自调节器VReg的当前电压Vint之间的差值DeltaV设定在预定极限内，以减小二次冲击电流 。
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公开(公告)号：US07049797B2
公开(公告)日：2006-05-23
申请号：US10676605
申请日：2003-10-02
申请人： Kenichi Fukui , Mitsuru Hiraki , Takayasu Ito , Isao Nakamura
发明人： Kenichi Fukui , Mitsuru Hiraki , Takayasu Ito , Isao Nakamura
CPC分类号： G05F1/56
摘要： In a semiconductor integrated circuit device, having a pair of voltage step-down power supply circuits for active and standby conditions, a first reference voltage is formed by amplifying a fixed voltage formed in a fixed voltage generating circuit with an amplifying circuit which can adjust the voltage gain having a resistance circuit and a switch controlled with a first trimming switch setting signal. An internal step-down voltage, when the internal circuit is in the active condition, is outputted from a first output buffer, which is activated with a first control signal. A second reference voltage is formed by adjusting a combination of threshold voltages of MOSFETs and a switch controlled with a second trimming switch setting signal; and, an internal step-down voltage, when the internal circuit is in the standby condition, is outputted with a second output buffer, which is activated with a second control signal.
摘要翻译： 在半导体集成电路器件中，具有用于有源和待机条件的一对降压电源电路，通过用放大电路放大固定电压产生电路中形成的固定电压来形成第一参考电压，该放大电路可以调节 具有电阻电路的电压增益和由第一微调开关设定信号控制的开关。 当内部电路处于活动状态时，内部降压电压从第一输出缓冲器输出，该第一输出缓冲器由第一控制信号激活。 通过调整MOSFET的阈值电压和由第二微调开关设置信号控制的开关的组合来形成第二参考电压; 并且当内部电路处于待机状态时，内部降压电压被第二输出缓冲器输出，该第二输出缓冲器由第二控制信号激活。
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公开(公告)号：US06584031B2
公开(公告)日：2003-06-24
申请号：US10107139
申请日：2002-03-28
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
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公开(公告)号：US06288967B1
公开(公告)日：2001-09-11
申请号：US09742078
申请日：2000-12-22
IPC分类号： G11C700
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
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公开(公告)号：US06271687B1
公开(公告)日：2001-08-07
申请号：US09531530
申请日：2000-03-21
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C706
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。
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