公开(公告)号：US07582901B2

公开(公告)日：2009-09-01

申请号：US11059651

申请日：2005-02-17

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

IPC分类号： H01L29/76

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。

公开(公告)号：US20050212082A1

公开(公告)日：2005-09-29

申请号：US11059651

申请日：2005-02-17

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。

公开(公告)号：US08174355B2

公开(公告)日：2012-05-08

申请号：US12167606

申请日：2008-07-03

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai

IPC分类号： H01C1/012

CPC分类号： H01C17/12 ,  H01C7/006 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/20 ,  H01L2924/0002 ,  Y10T29/49099 ,  H01L2924/00

摘要： A resistor R1 formed by forming a first resistor layer 5a of 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.

摘要翻译： 形成电阻器R1，其形成为包括氮浓度小于30at％的氮化钽膜和20nm厚度的第二电阻层5a，其厚度为20nm，第一电阻层5a包括氮浓度为氮的氮化钽膜 通过使用钽作为溅射靶材料并使用氩和氮的气体混合物作为溅射气体的反应性DC溅射法连续地为30at％或更多，然后制造第一和第二电阻层，其中电阻变化 即使在互连步骤中施加热负荷时，通过设置氮浓度为30at％以上的上部区域，也可以将电阻器的比例抑制在小于1％。

公开(公告)号：US08048735B2

公开(公告)日：2011-11-01

申请号：US11764073

申请日：2007-06-15

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai

IPC分类号： H01L21/8242

CPC分类号： H01L21/76811 ,  H01L21/76831 ,  H01L23/5223 ,  H01L28/55 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.

摘要翻译： 本发明提供一种使用高k电介质膜的MIM电容器，其防止MIM电容器的击穿场强的劣化并抑制漏电流的增加。 MIM电容器包括第一金属互连，制造的电容膜，制造的上电极和第三金属互连。 MIM电容器通过形成包含氧化硅的层间电介质膜来覆盖第一金属互连，然后在层间电介质膜中形成第一开口到与层间绝缘膜中的通孔层对应的区域 第一金属互连，以便不暴露第一金属互连的上表面，然后在第一开口的内部形成第二开口，以露出第一金属互连的表面，然后形成电容膜和第三金属 互连。

公开(公告)号：US20090302993A1

公开(公告)日：2009-12-10

申请号：US12481384

申请日：2009-06-09

申请人： TSUYOSHI FUJIWARA ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

发明人： TSUYOSHI FUJIWARA ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

IPC分类号： H01C1/012

CPC分类号： H01L23/5228 ,  H01L27/0688 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。

公开(公告)号：US08212649B2

公开(公告)日：2012-07-03

申请号：US13238056

申请日：2011-09-21

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

IPC分类号： H01C1/12

CPC分类号： H01L23/5228 ,  H01L27/0688 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。

公开(公告)号：US08040214B2

公开(公告)日：2011-10-18

申请号：US12481384

申请日：2009-06-09

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Kenichi Takeda ,  Hiromi Shimamoto

IPC分类号： H01C1/12

CPC分类号： H01L23/5228 ,  H01L27/0688 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。

公开(公告)号：US07122900B2

公开(公告)日：2006-10-17

申请号：US10276776

申请日：2001-05-28

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。 第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）表示的烷氧基硅烷的气体混合物形成（n为 1〜3的整数，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括具有高可靠性和较少布线延迟时间的铜布线的半导体器件。

公开(公告)号：US07947596B2

公开(公告)日：2011-05-24

申请号：US11526754

申请日：2006-09-26

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/00

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）nSiH 4-n表示的烷氧基硅烷（n为整数）的气体混合物形成 1〜3的范围，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括具有高可靠性和较少布线延迟时间的铜布线的半导体器件。

公开(公告)号：US20070018330A1

公开(公告)日：2007-01-25

申请号：US11526754

申请日：2006-09-26

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。 第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）表示的烷氧基硅烷的气体混合物形成（n为 1〜3的整数，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括高可靠性和较少布线延迟时间的铜布线的半导体器件。