公开(公告)号：US07947596B2

公开(公告)日：2011-05-24

申请号：US11526754

申请日：2006-09-26

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/00

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）nSiH 4-n表示的烷氧基硅烷（n为整数）的气体混合物形成 1〜3的范围，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括具有高可靠性和较少布线延迟时间的铜布线的半导体器件。

公开(公告)号：US20070018330A1

公开(公告)日：2007-01-25

申请号：US11526754

申请日：2006-09-26

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。 第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）表示的烷氧基硅烷的气体混合物形成（n为 1〜3的整数，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括高可靠性和较少布线延迟时间的铜布线的半导体器件。

公开(公告)号：US07122900B2

公开(公告)日：2006-10-17

申请号：US10276776

申请日：2001-05-28

申请人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

发明人： Kenichi Takeda ,  Daisuke Ryuzaki ,  Kenji Hinode ,  Toshiyuki Mine

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813

摘要： A semiconductor device according to this invention comprises a substrate 100 in which semiconductor elements are formed, a first conductor 301 at least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layer 203 covering at least a portion of the first conductor 301. The first insulative diffusion barrier layer 203 is formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)nSiH4−n (n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

摘要翻译： 根据本发明的半导体器件包括其中形成有半导体元件的基板100，其外围表面的至少一部分由包含铜作为主要成分的材料制成的第一导体301和第一绝缘扩散阻挡层 层203覆盖第一导体301的至少一部分。 第一绝缘扩散阻挡层203通过使用至少含有由通式（RO）表示的烷氧基硅烷的气体混合物形成（n为 1〜3的整数，R表示烷基，芳基或其衍生物）和通过等离子体CVD的氧化性气体。 因此，可以提供包括具有高可靠性和较少布线延迟时间的铜布线的半导体器件。

公开(公告)号：US07582901B2

公开(公告)日：2009-09-01

申请号：US11059651

申请日：2005-02-17

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

IPC分类号： H01L29/76

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。

公开(公告)号：US20050212082A1

公开(公告)日：2005-09-29

申请号：US11059651

申请日：2005-02-17

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。

公开(公告)号：US20120211718A1

公开(公告)日：2012-08-23

申请号：US13440225

申请日：2012-04-05

申请人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08125012B2

公开(公告)日：2012-02-28

申请号：US11639134

申请日：2006-12-15

申请人： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

发明人： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42344 ,  H01L29/512 ,  H01L29/513 ,  H01L29/792 ,  Y10S438/954

摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.

摘要翻译： 通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。 通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。 通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。 在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。 电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

公开(公告)号：US07863134B2

公开(公告)日：2011-01-04

申请号：US12695271

申请日：2010-01-28

申请人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

发明人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L29/4234 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/792

摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。

公开(公告)号：US07682990B2

公开(公告)日：2010-03-23

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed.For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20090134449A1

公开(公告)日：2009-05-28

申请号：US12273308

申请日：2008-11-18

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。