公开(公告)号：US20090263509A1

公开(公告)日：2009-10-22

申请号：US10598411

申请日：2005-02-25

申请人： Kenji Sakamoto ,  Toshiyuki Mukaiyama ,  Kazuyuki Hori ,  Saori Takahashi

发明人： Kenji Sakamoto ,  Toshiyuki Mukaiyama ,  Kazuyuki Hori ,  Saori Takahashi

IPC分类号： A01N43/16 ,  A01N65/12 ,  C07D311/04

CPC分类号： A61Q17/005 ,  A01N43/16 ,  A01N65/20 ,  A23B4/20 ,  A23L3/3544 ,  A61K8/498 ,  A61K8/97 ,  A61K36/48 ,  A61K2800/52 ,  A61Q1/10 ,  A61Q5/00 ,  A61Q5/02 ,  A61Q15/00 ,  A61Q19/00 ,  A61Q19/10 ,  C07D311/58 ,  C07D311/64 ,  A61K2300/00

摘要： The problems to be solved by the invention are to provide antibacterial agents originated from natural products that are safe for regular use with potent antibacterial activity, and antibacterial compositions containing said antibacterial agents. Antibacterial agents containing Eysenhardtia adenostylis extract or isoflavan compounds are a solution to the problem. Also antibacterial agents containing Eysenhardtia adenostylis extract or isoflavan compounds as active ingredients. The antibacterial agents can be applied to products such as cosmetics, including quasi-drugs, pharmaceuticals and foods. Further, antibacterial compositions containing these antibacterial agents, Eysenhardtia adenostylis extract or isoflavan compounds, and other compositions such as cosmetics, including quasi-drugs, pharmaceuticals and foods.

摘要翻译： 本发明要解决的问题是提供源自天然产物的抗菌剂，其具有有效抗菌活性的常规使用的安全性，以及含有所述抗菌剂的抗菌组合物。 含有Eysenhardtia adenostylis提取物或异黄酮化合物的抗菌剂是解决问题的方法。 还含有抗菌药物，其中含有Eysenhardtia adenostylis提取物或异黄烷化合物作为活性成分。 抗菌剂可用于化妆品，包括准药，药品，食品等产品。 此外，含有这些抗菌剂，扁桃体提取物或异黄酮化合物的抗菌组合物，以及其他组合物，例如化妆品，包括准药物，药物和食品。

公开(公告)号：US07817746B2

公开(公告)日：2010-10-19

申请号：US11829405

申请日：2007-07-27

申请人： Kazuyuki Hori ,  Hideaki Arai ,  Shouhei Murakami

发明人： Kazuyuki Hori ,  Hideaki Arai ,  Shouhei Murakami

IPC分类号： H04L25/03

CPC分类号： H04B1/707 ,  H04B2201/70706 ,  H04L27/2624

摘要： A peak factor reduction unit that never allow peak factor reproduction even when interpolation is done in a succeeding stage. The unit detects a local maximum value of amplitude components from an input complex signal and supplies a complex signal that passes a band limiting baseband filter and an interpolation filter to a correction signal generation unit for generating a correction signal used for peak factor reduction and reduces a peak factor of the input complex signal with use of the correction signal generated from an interpolated complex signal.

摘要翻译： 峰值因子降低单元，即使在后续阶段进行插值，也不允许峰值因子再现。 该单元从输入复合信号中检测振幅分量的局部最大值，并将通过带限基带滤波器和内插滤波器的复信号提供给校正信号生成单元，用于产生用于峰值因子减小的校正信号，并减少 使用从内插复数信号生成的校正信号的输入复信号的峰值因子。

公开(公告)号：US07800452B2

公开(公告)日：2010-09-21

申请号：US11976408

申请日：2007-10-24

申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation.This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US20080219372A1

公开(公告)日：2008-09-11

申请号：US12027035

申请日：2008-02-06

申请人： Kazuyuki Hori ,  Yuji Ishida ,  Shouhei Murakami ,  Kenji Yanagi

发明人： Kazuyuki Hori ,  Yuji Ishida ,  Shouhei Murakami ,  Kenji Yanagi

IPC分类号： H04L5/12

CPC分类号： H04L27/2614 ,  H04L27/2624

摘要： An OFDM modulator having a peak factor reduction function. The OFDM modulator has a peak factor reduction unit between an IFFT unit and a guard interval insertion unit thereof. The peak factor reduction unit converts a complex signal X1 outputted from the IFFT unit into a complex signal X2 with a reduced peak factor based on subcarrier map information. The peak factor reduction unit generates a peak factor reduction signal by a linear combination of complex exponential functions that correspond to subcarrier frequencies to be used for wave transmission, as bases. The peak factor reduction signal is derived by repetition of, for example, a weighted least squares method or convolution processing by a fast Fourier transform.

摘要翻译： 一种具有峰值因子减小函数的OFDM调制器。 OFDM调制器在IFFT单元与其保护间隔插入单元之间具有峰值因子减小单元。 峰值因子降低单元基于副载波映射信息将从IFFT单元输出的复信号X 1以具有降低的峰值因子的复信号X 2转换。 峰值因子降低单元通过对应于用于波传输的副载波频率的复指数函数的线性组合作为基础产生峰值因子减小信号。 通过重复例如加权最小二乘法或快速傅里叶变换的卷积处理来导出峰值因子降低信号。

公开(公告)号：US20080061890A1

公开(公告)日：2008-03-13

申请号：US11976408

申请日：2007-10-24

申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US08280442B2

公开(公告)日：2012-10-02

申请号：US12485554

申请日：2009-06-16

申请人： Haruo Nakano ,  Kazuyuki Hori ,  Masanori Taira ,  Takahiro Chiba ,  Yasuyuki Magara

发明人： Haruo Nakano ,  Kazuyuki Hori ,  Masanori Taira ,  Takahiro Chiba ,  Yasuyuki Magara

IPC分类号： H04B17/00 ,  H04B1/10 ,  H04B1/38 ,  H04B3/46 ,  H04Q1/20 ,  H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04L1/00 ,  H04L25/08 ,  G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L12/26

CPC分类号： H04B17/0085 ,  H04B17/327 ,  H04W24/06

摘要： Even if a receiver has a normal gain and a lowered intermodulation distortion characteristics, a fault detection is possible. A test signal transmitter sends a test signal having at least two frequencies to a radio receiver through a coupler. A digital signal processing section receives a signal which includes an IM3 component generated by the radio receiver and measures the electric power of fundamental wave components and the IM3 component. Then, the digital signal processing section calculates the gain of the radio receiver and IIP3, which is an index for intermodulation distortion characteristics, of the radio receiver 207 from the calculated electric power. A base station control section determines whether the gain and IIP3 of the radio receiver fall in predetermined ranges to determine whether the radio receiver works normally or has a fault.

摘要翻译： 即使接收机具有正常增益和降低的互调失真特性，故障检测也是可能的。 测试信号发射器通过耦合器向无线电接收机发送具有至少两个频率的测试信号。 数字信号处理部分接收包括由无线电接收机产生的IM3分量的信号并测量基波分量和IM3分量的电功率。 然后，数字信号处理部从计算出的电力计算无线电接收机207的增益和作为互调失真特性的指标的IIP3。 基站控制部分确定无线电接收机的增益和IIP3是否落在预定范围内，以确定无线电接收机是正常工作还是有故障。

公开(公告)号：US08175198B2

公开(公告)日：2012-05-08

申请号：US12338391

申请日：2008-12-18

申请人： Kazuyuki Hori

发明人： Kazuyuki Hori

IPC分类号： H03D1/00

CPC分类号： G06F17/15 ,  H03H17/0254 ,  H04B1/7093

摘要： A matched filter and receiver is provided to delete the tap coefficients of a matched filter used in an OFDM receiver. In the matched filter and receiver, a transmitting signal is generated by using a symmetric series (Y) obtained from C[k]=exp[j*π*M/N*(k+0.5)^2], where X=[0, C[N/2], C[N/2+1], . . . , C[N−1], 0, 0, . . . , 0, C[0], C[1], . . . , C[N/2−1]], and Y=inverse FFT (X) as a base symbol. The matched filter, which detects the signal, reduces the number of multipliers by using the coefficient symmetric property.

摘要翻译： 提供匹配滤波器和接收机来删除在OFDM接收机中使用的匹配滤波器的抽头系数。 在匹配滤波器和接收机中，通过使用从C [k] = exp [j *＆pgr; * M / N *（k + 0.5）^ 2]获得的对称序列（Y）生成发送信号，其中X = [0，C [N / 2]，C [N / 2 + 1]，。 。 。 ，C [N-1]，0,0，...。 。 。 ，0，C [0]，C [1]，。 。 。 ，C [N / 2-1]]，Y =逆FFT（X）作为基本符号。 检测信号的匹配滤波器通过使用系数对称属性来减少乘法器的数量。

公开(公告)号：US20110096865A1

公开(公告)日：2011-04-28

申请号：US12929083

申请日：2010-12-29

申请人： Kazuyuki Hori ,  Shouhei Murakami ,  Yuji Ishida ,  Tomoya Uchiike ,  Yoshiaki Hasegawa

发明人： Kazuyuki Hori ,  Shouhei Murakami ,  Yuji Ishida ,  Tomoya Uchiike ,  Yoshiaki Hasegawa

IPC分类号： H04L27/04

CPC分类号： H04L27/368 ,  H03F1/3247 ,  H03F1/3258

摘要： There is a need for effectively compensating distortion when a predistortion transmitter is subject to not only a memory effect due to nonlinearity of an amplifier, but also a modulator's DC offset, IQ unbalance, or local quadrature error. A predistortor to be used is a polynomial predistortor including a polynomial basis generation portion and an inner product calculation portion. The polynomial basis generation portion delays a real part and an imaginary part of a complex input signal Sx=Ix+jQx for up to M samples to generate 2(M+1) signals, duplicately combines these signals to generate monomials having maximum degree N, and outputs, as a basis vector, all or part of the monomials depending or needs. The inner product calculation portion performs an inner product calculation using a coefficient vector, i.e., a set of complex numbers sized equally to the basis vector to find a polynomial value and outputs the value as a complex signal.

公开(公告)号：US07920652B2

公开(公告)日：2011-04-05

申请号：US11005073

申请日：2004-12-07

申请人： Shigenori Hayase ,  Kazuyuki Hori

发明人： Shigenori Hayase ,  Kazuyuki Hori

IPC分类号： H04L27/00

CPC分类号： H03D7/163 ,  H03D3/245 ,  H04L27/3863

摘要： To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.

摘要翻译： 检测正交解调器的同相和正交信号之间的相位失配。 可以使用通过低通滤波器去除乘法器的输出的高频分量而获得的信号来检测相位失配，该输出是通过第一高通滤波器去除低频分量的同相信号的乘积 通过第二高通滤波器去除低频分量的正交信号。

公开(公告)号：US20050153669A1

公开(公告)日：2005-07-14

申请号：US11033905

申请日：2005-01-13

申请人： May Suzuki ,  Kazuyuki Hori ,  Takashi Yano

发明人： May Suzuki ,  Kazuyuki Hori ,  Takashi Yano

IPC分类号： H03G3/30 ,  H04B1/04 ,  H04L7/02 ,  H04L27/00 ,  H03F3/38 ,  H04B1/02

CPC分类号： H04B1/0475 ,  H03F1/3247 ,  H03F1/3282 ,  H03F1/34 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/451 ,  H04B1/0483 ,  H04B2001/0433 ,  H04L7/0054

摘要： The linearity of a transmission signal is improved in a wireless communication device by adjusting a delay difference between paths of two signals that are combined into one after modulation through the paths of different delay amounts, such as an r signal and a θ signal in EER. A transmitter includes: a DA converter unit which converts, into analog signals, separated input digital signals; a combiner which combines the analog signals obtained through the DA conversion with each other; an distributor which extracts a feedback signal; an AD converter which converts the feedback signal into a digital signal; an oscillator unit which supplies clock signals to the converters; a first separation unit which separates the feedback signal; and a comparator unit which compares the input signal and the feedback signal, wherein the oscillator unit controls the output clock signals based on a result of the comparison.

摘要翻译： 通过调整通过不同延迟量的路径（例如EER中的r信号和θ信号）组合成一个后调制的两个信号的路径之间的延迟差，在无线通信设备中改善了传输信号的线性度。 发射机包括：DA转换器单元，其将模拟信号转换成分离的输入数字信号; 组合器，其将通过DA转换获得的模拟信号彼此组合; 提取反馈信号的分配器; 将反馈信号转换为数字信号的AD转换器; 振荡器单元，向转换器提供时钟信号; 分离反馈信号的第一分离单元; 以及比较器单元，其比较所述输入信号和所述反馈信号，其中所述振荡器单元基于所述比较的结果来控制所述输出时钟信号。