公开(公告)号：US4908752A

公开(公告)日：1990-03-13

申请号：US328182

申请日：1989-03-24

申请人： Eiichi Suzuki ,  Kenji Yokoyama ,  Masao Noro

发明人： Eiichi Suzuki ,  Kenji Yokoyama ,  Masao Noro

IPC分类号： H02M3/07 ,  H02M3/155

CPC分类号： H02M3/07 ,  H02M2001/009 ,  Y10S323/908

摘要： A DC-to-DC voltage-increasing power source suitable for use in an audio device mounted on an automobile or a portable type audio device includes a DC power source, a drive pulse generation circuit for generating drive pulses which are in 180 degree phase relationship, a switching circuit of a push-pull connection supplied with operating voltage from the DC power source and driven between an on-state and an off-state in response to the drive pulses, a charge and discharge circuit including capacitors charged by being connected in parallel to the DC power source and discharging a sum voltage by being connected in series to the DC power source and an output takeout circuit for taking out this sum voltage as a voltage-increasing DC output. The switching circuit is constructed of voltage-controlled type elements whose on-state is changed in response to the level of an on-pulse in the drive pulses and the drive pulse generation circuit includes a pulse level changing circuit for changing the level of the on-pulse. in one aspect of the invention, the switching circuit includes a variable time constant circuit for transmitting an on-pulse with a relatively large time constant and an off-pulse with a relatively small time constant.

公开(公告)号：US5280543A

公开(公告)日：1994-01-18

申请号：US54862

申请日：1993-04-27

申请人： Kenji Yokoyama ,  Masao Noro

发明人： Kenji Yokoyama ,  Masao Noro

IPC分类号： H04R3/00

CPC分类号： H04R3/002

摘要： An acoustic apparatus comprises a cabinet, and a loudspeaker unit and a driving apparatus disposed in the cabinet. The acoustic apparatus is driven by an external power amplifier which normally constant-voltage-drives a conventional loudspeaker. The driving apparatus has a power amplifier circuit and a transfer function control circuit, and drives the loudspeaker unit in cooperation with the external power amplifier. The driving apparatus generates an electric energy corresponding to an increase in energy from that which is required in a normal constant-voltage-driving, the increase being produced by an operation of the transfer function control circuit, and the generated energy is inputted to the loudspeaker unit. By means of the above, when the acoustic apparatus is driven by the external power amplifier, an internal resistance of the loudspeaker unit is substantially cancelled or reduced, and an improvement of the electro-acoustic transducing characteristics of the loudspeaker unit or a loudspeaker system is achieved.

摘要翻译： 一种声学装置，包括一个机柜，一个扬声器单元和一个设在机柜中的驱动装置。 声学装置由外部功率放大器驱动，外部功率放大器通常对常规扬声器进行恒压驱动。 驱动装置具有功率放大电路和传递功能控制电路，并与外部功率放大器协同驱动扬声器单元。 驱动装置产生与正常恒压驱动中所需的能量增加相对应的电能，通过传递函数控制电路的操作产生增加，并且所产生的能量被输入到扬声器 单元。 通过上述，当声学装置由外部功率放大器驱动时，扬声器单元的内部电阻基本上被抵消或减小，并且扬声器单元或扬声器系统的电声换能特性的改善是 实现了

公开(公告)号：US20090041268A1

公开(公告)日：2009-02-12

申请号：US12188835

申请日：2008-08-08

申请人： Masaya KANO ,  Hironari Kawai ,  Masao Noro

发明人： Masaya KANO ,  Hironari Kawai ,  Masao Noro

IPC分类号： H03F21/00

CPC分类号： H03F3/181 ,  H03F1/0211 ,  H03F1/0277 ,  H03F1/34 ,  H03F2200/03 ,  H03F2200/393

摘要： An amplification system of the invention can decrease power consumption in a power amplification section if the power amplification section need not be used. The power consumption in the power amplification section can be decreased by shutting off power feed into a voltage amplification stage by a power control section, and the power feed state into a power amplification stage from a power supply section is not changed. Thus, power feed into the voltage amplification stage of the circuit wherein a large current does not flow needs only to be controlled using limiter means also used for a different application, so that the power consumption of the power amplification section can be decreased without the need for enlarging the circuit scale, with saved space, and simply.

摘要翻译： 如果不需要使用功率放大部分，本发明的放大系统可以降低功率放大部分的功耗。 功率放大部分的功率消耗可以通过关闭由功率控制部分进入电压放大级的馈电来降低，并且从电源部分进入功率放大级的馈电状态不改变。 因此，不需要大电流的电路的电压放大级的馈电仅需要使用也用于不同应用的限幅器装置进行控制，从而可以在不需要的情况下降低功率放大部分的功耗 用于扩大电路规模，节省空间，简单。

公开(公告)号：US06937091B2

公开(公告)日：2005-08-30

申请号：US10632248

申请日：2003-08-01

申请人： Yasuomi Tanaka ,  Masao Noro

发明人： Yasuomi Tanaka ,  Masao Noro

IPC分类号： H03K17/687 ,  H03F3/217 ,  H03F3/30 ,  H03F3/38

CPC分类号： H03F3/2171

摘要： A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP−). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP−), to a driving circuit (304). As a result, the driving circuits (304, 305) complementarily drive power-MOS transistors (401, 402).

摘要翻译： 互补信号发生电路（301）从PWM信号产生第一互补信号（S1，S2）。 信号转换电路（302）将第一互补信号转换成具有基于负电源（VPP-）的电压分量的第二互补信号（S 3，S 4或S 5，S 6）。 在第二互补信号中，信号（S 3，S 4）被提供给驱动电路（305），并且信号（S 5，S 6）被提供给电流驱动电路（303）。 响应于信号（S 5，S 6），电流驱动电路将具有指向负电源（VPP-）的电流分量的第三互补信号（H 3，H 4）输出到驱动电路 304）。 结果，驱动电路（304,305）互补驱动功率MOS晶体管（401,402）。

公开(公告)号：US06903607B2

公开(公告)日：2005-06-07

申请号：US10623826

申请日：2003-07-21

申请人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka

发明人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka

IPC分类号： H03F3/45

CPC分类号： H03F3/45188

摘要： An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.

摘要翻译： 运算放大器具有差分放大级，该差分放大级包括一对第一PMOS晶体管，用于输入信号，该第一PMOS晶体管布置在与第一恒流源耦合的正电压源和负电压源之间，其中高耐压型的第二PMOS晶体管 其栅极被偏置到规定的电压，被布置在与负载电阻器一起位于第一PMOS晶体管和负电压源之间的电流路径上。 这里，第一PMOS晶体管的漏极电压的每一个被限制为比栅极阈值电压高于规定电压的一定值。 因此，即使当第一PMOS晶体管由正常耐压型构成时，也可以可靠地防止施加到第一PMOS晶体管的电压超过其击穿电压，从而避免不必要地降低S / N比。

公开(公告)号：US06707337B2

公开(公告)日：2004-03-16

申请号：US10253077

申请日：2002-09-24

申请人： Masao Noro

发明人： Masao Noro

IPC分类号： H03F338

CPC分类号： H03F3/2173

摘要： Differential integrator circuit integrates a differential between a difference between a signal supplied from a first signal source and a feedback signal of amplifier output and a difference between a signal supplied from a second signal source and a feedback signal of the amplifier output. The signal supplied from the second signal source is opposite in phase from the signal supplied from the first signal source. Thus, the integrator circuit outputs two integrated signals of different polarities. Comparator compares the two integrated signals from the integrator circuit to thereby output a PWM signal. First driver circuit amplifies the PWM signal and outputs the amplified PWM signal with inverted phase, and a second driver circuit amplifies the PWM signal and outputs the amplified PWM signal with noninverted phase. First switching circuit is driven by the output of the first driver circuit, while a second switching circuit is driven by the output of the second driver circuit.

摘要翻译： 差分积分器电路将从第一信号源提供的信号与放大器输出的反馈信号之间的差与由第二信号源提供的信号与放大器输出的反馈信号之间的差进行积分。 从第二信号源提供的信号与从第一信号源提供的信号的相位相反。 因此，积分器电路输出具有不同极性的两个积分信号。 比较器比较来自积分器电路的两个积分信号，从而输出PWM信号。 第一驱动电路放大PWM信号并输出​​反相放大的PWM信号，第二驱动电路放大PWM信号并以非反相输出放大的PWM信号。 第一开关电路由第一驱动电路的输出驱动，而第二开关电路由第二驱动电路的输出驱动。

公开(公告)号：US06703958B2

公开(公告)日：2004-03-09

申请号：US09870153

申请日：2001-05-30

申请人： Masao Noro

发明人： Masao Noro

IPC分类号： H03M112

CPC分类号： H03M1/48

摘要： A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.

摘要翻译： 将从外部模拟信号源顺序产生的外部模拟信号转换成n位数字数据信号（n为2以上的整数）的高效率模数（A / D）转换电路包括： 一个将n位数字数据信号转换为模拟信号并从第一输出端输出模拟信号的数/模（D / A）转换器电路，比较器，用于比较提供的外部模拟信号的信号电平 从具有从第一输出端子输出的模拟信号的信号电平的外部装置，以及数字积分电路，对从比较器输出的1位数字数据信号进行数字积分，从而产生n位数字数据信号。

公开(公告)号：US06696891B2

公开(公告)日：2004-02-24

申请号：US10251169

申请日：2002-09-20

申请人： Masao Noro ,  Yasuhiko Sekimoto

发明人： Masao Noro ,  Yasuhiko Sekimoto

IPC分类号： H03F338

CPC分类号： H03F3/2171 ,  H03F2200/331

摘要： A class D amplifier includes: an integrating circuit (1) which integrates an input signal; a flash A/D converter (2) which A/D converts an output signal of the integrating circuit; a waveform converting circuit (3) which produces a PWM signal based on an output of the flash A/D converter; a switching circuit which is includes a pair of MOS transistors (5, 6) connected between a first power source and a second power source, the junction point P of the pair of MOS transistors being connected to a loudspeaker (51); a driving circuit (4) which drives the pair of MOS transistors on the basis of the PWM signal; and a feedback resistor (RNF) which is connected between the junction point P and the input side of the integrating circuit, and negatively feeds back the output signal of the amplifier.

摘要翻译： D类放大器包括：积分电路（1），其对输入信号进行积分; 闪存A / D转换器（2），其对所述积分电路的输出信号进行A / D转换; 波形转换电路（3），其基于闪存A / D转换器的输出产生PWM信号; 开关电路，包括连接在第一电源和第二电源之间的一对MOS晶体管（5,6），所述一对MOS晶体管的接点P连接到扬声器（51）; 驱动电路（4），其基于所述PWM信号驱动所述一对MOS晶体管; 以及连接在积分电路的接合点P和输入侧之间的反馈电阻器（RNF），并且负反馈放大器的输出信号。

公开(公告)号：US06445320B1

公开(公告)日：2002-09-03

申请号：US09492442

申请日：2000-01-27

申请人： Masao Noro ,  Akira Sogo ,  Ryo Kamiya

发明人： Masao Noro ,  Akira Sogo ,  Ryo Kamiya

IPC分类号： H03M162

CPC分类号： H03M3/49

摘要： An A/D conversion apparatus is provided, which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels. An input gain control device controls gain of an input signal based on a control signal. A &Dgr;&Sgr; modulator carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit. A detecting device detects a peak value of the input signal based on the data of one bit. A gain control device generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range. To effectively reduce noise of the output digital signal while securing a wide dynamic range of A/D conversion, the &Dgr;&Sgr; modulator may also control the gain of the input signal based on the control signal to a predetermined value (1/A) smaller than 1, and the decimation circuit may have a gain of a second predetermined value (A) for compensating for the gain of the input signal controlled to the predetermined value (1/A).

摘要翻译： 提供了一种A / D转换装置，其能够通过在预定电平之间适当地切换输入模拟信号的输入增益，以简单的结构确保宽动态范围的A / D转换。 输入增益控制装置基于控制信号来控制输入信号的增益。 DELTASIGMA调制器对输入信号进行过采样，该输入信号的增益由输入增益控制装置控制，以将输入信号转换成一位的数据。 检测装置根据一位的数据来检测输入信号的峰值。 增益控制装置基于由检测装置检测的峰值以使得其控制增益的输入信号落在预定范围内的方式产生控制信号。 为了有效地降低输出数字信号的噪声，同时确保宽的动态范围的A / D转换，DELTASIGMA调制器还可以基于控制信号将输入信号的增益控制到小于1的预定值（1 / A） ，并且抽取电路可以具有用于补偿被控制到预定值（1 / A）的输入信号的增益的第二预定值（A）的增益。

公开(公告)号：US5757299A

公开(公告)日：1998-05-26

申请号：US533764

申请日：1995-09-26

申请人： Masao Noro ,  Yusuke Yamamoto ,  Toshio Maejima

发明人： Masao Noro ,  Yusuke Yamamoto ,  Toshio Maejima

IPC分类号： H03M3/02

CPC分类号： H03M3/444 ,  H03M3/43

摘要： An analog-digital converter comprises a .DELTA. .SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA. .SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA. .SIGMA. modulator comprises at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.

摘要翻译： 模数转换器包括串联连接的DELTA SIGMA调制器，数字滤波器，高通滤波器和乘法器。 模拟输入通过DELTA SIGMA调制器转换成串行位串，为其设置增益'1 / A'。 数字滤波器从串行比特串中提取与模拟输入相对应的低频分量，因此低频分量转换为并行位数字数据。 高通滤波器从数字滤波器的输出中去除直流偏移分量; 然后，通过乘法器将其输出乘以缩放增益“A”，从而产生数字输出。 DELTA SIGMA调制器包括串联连接的至少三个开关电容积分器和一位量化器以及单采样延迟电路。 由一位量化器产生的一位输出由单采样延迟电路延迟，其中输出被传送到每个开关电容积分器。 每个开关电容积分器使用由CMOS运算放大器和至少一个幅度限制电路配置的CMOS差分放大器来配置。 限幅电路由两个PMOS晶体管和两个以二极管连接方式并联连接的NMOS晶体管构成; 并且该电路被提供以通过稳定其工作点来限制CMOS差分放大器的输出的幅度。