公开(公告)号：US06903607B2

公开(公告)日：2005-06-07

申请号：US10623826

申请日：2003-07-21

申请人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka

发明人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka

IPC分类号： H03F3/45

CPC分类号： H03F3/45188

摘要： An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.

摘要翻译： 运算放大器具有差分放大级，该差分放大级包括一对第一PMOS晶体管，用于输入信号，该第一PMOS晶体管布置在与第一恒流源耦合的正电压源和负电压源之间，其中高耐压型的第二PMOS晶体管 其栅极被偏置到规定的电压，被布置在与负载电阻器一起位于第一PMOS晶体管和负电压源之间的电流路径上。 这里，第一PMOS晶体管的漏极电压的每一个被限制为比栅极阈值电压高于规定电压的一定值。 因此，即使当第一PMOS晶体管由正常耐压型构成时，也可以可靠地防止施加到第一PMOS晶体管的电压超过其击穿电压，从而避免不必要地降低S / N比。

公开(公告)号：US06903577B2

公开(公告)日：2005-06-07

申请号：US10439492

申请日：2003-05-16

申请人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka ,  Yasuhiko Sekimoto ,  Masamitsu Hirano

发明人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka ,  Yasuhiko Sekimoto ,  Masamitsu Hirano

IPC分类号： H03K5/00 ,  H03K5/14 ,  H03K19/0175

CPC分类号： H03K5/13 ,  H03K2005/00156

摘要： An input signal (SIN) is inverted by an inverter (101), and the inverted input signal is entered into a tri-state type inverter (104). An output portion of this inverter is connected via a delay path (105) to an input portion of an operational amplifier (106). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit (103) controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S11) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S16) output from the operational amplifier. As a result, an amplitude of a signal (S15) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (106), and a delay time is made constant.

摘要翻译： 输入信号（SIN）由逆变器（101）反相，反相输入信号进入三态逆变器（104）。 该反相器的输出部分经由延迟路径（105）连接到运算放大器（106）的输入部分。 该运算放大器相对于输入的信号具有滞后特性。 异或门电路（103）控制在接收到通过反相输入信号获得的信号（S11）时将逆变器的输出状态设置为低阻抗状态，并且控制将逆变器的输出状态设置为 在接收到从运算放大器输出的信号（S16）时的高阻抗状态。 结果，响应于运算放大器（106）的滞后特性，信号（S 15）的幅度被限制到恒定幅度，并且延迟时间变得恒定。

公开(公告)号：US06448856B2

公开(公告)日：2002-09-10

申请号：US09773646

申请日：2001-01-31

申请人： Masao Noro ,  Nobuaki Tsuji

发明人： Masao Noro ,  Nobuaki Tsuji

IPC分类号： H03G310

CPC分类号： H03G1/0035 ,  H03G3/001

摘要： An electronic volume circuit is provided, which can be driven by a single power source and can therefore be formed by an LSI that can be fabricated in a simple manner using an oxide film and a junction process for a single power source. A first amplifying circuit attenuates the amplitude of a bipolar input signal and converts the attenuated input signal to a unipolar signal, and a variable resistor device controls the degree of attenuation of the first amplifying circuit based on an externally supplied signal.

摘要翻译： 提供了一种电子体积电路，其可以由单个电源驱动，并且因此可以由可以使用氧化膜和单个电源的接合处理以简单的方式制造的LSI形成。 第一放大电路衰减双极性输入信号的幅度，并将衰减的输入信号转换为单极性信号，可变电阻器件根据外部提供的信号来控制第一放大电路的衰减程度。

公开(公告)号：US07075123B2

公开(公告)日：2006-07-11

申请号：US10968685

申请日：2004-10-19

申请人： Nobuaki Tsuji ,  Masao Noro ,  Terumitsu Maeno ,  Seiji Hirade

发明人： Nobuaki Tsuji ,  Masao Noro ,  Terumitsu Maeno ,  Seiji Hirade

IPC分类号： H01L29/74 ,  H01L23/62

CPC分类号： H01L27/0255 ,  H01L27/0259 ,  H01L27/0288

摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

摘要翻译： 横向PNP晶体管PB和横向NPN晶体管NB串联连接在输入端子和参考电位（地电位）之间。 在晶体管PB中，形成二极管D 1 1。 在晶体管NB中，形成二极管D 3 3。 当输入+2000V的ESD时，晶体管NB导通，而当输入-2000V的ESD时，晶体管PB导通。 能够输入的正信号的电平受到二极管D 3 3的反向击穿电压（例如，18至50V）的限制，而能够输入的负信号的电平为 受二极管D 1 1的反向击穿电压（例如，13至15V）的限制。

公开(公告)号：US20050051847A1

公开(公告)日：2005-03-10

申请号：US10968685

申请日：2004-10-19

申请人： Nobuaki Tsuji ,  Masao Noro ,  Terumitsu Maeno ,  Seiji Hirade

发明人： Nobuaki Tsuji ,  Masao Noro ,  Terumitsu Maeno ,  Seiji Hirade

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/74

CPC分类号： H01L27/0255 ,  H01L27/0259 ,  H01L27/0288

摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

公开(公告)号：US06847059B2

公开(公告)日：2005-01-25

申请号：US09982335

申请日：2001-10-18

申请人： Nobuaki Tsuji ,  Masao Noro ,  Terumitsu Maeno ,  Seiji Hirade

发明人： Nobuaki Tsuji ,  Masao Noro ,  Terumitsu Maeno ,  Seiji Hirade

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/74 ,  H01L23/62

CPC分类号： H01L27/0255 ,  H01L27/0259 ,  H01L27/0288

摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

摘要翻译： 横向PNP晶体管PB和横向NPN晶体管NB串联连接在输入端子和参考电位（地电位）之间。 在晶体管PB中形成二极管D1。 在晶体管NB中，形成二极管D3。 当输入+2000V的ESD时，晶体管NB导通，而当输入-2000V的ESD时，晶体管PB导通。 能够输入的正信号的电平受到二极管D3的反向击穿电压（例如，18至50V）的限制，而能够被输入的负信号的电平受到反向击穿电压的限制（例如， ，13〜15V）。

公开(公告)号：US06791405B2

公开(公告)日：2004-09-14

申请号：US10400357

申请日：2003-03-27

申请人： Nobuaki Tsuji ,  Masao Noro

发明人： Nobuaki Tsuji ,  Masao Noro

IPC分类号： H03F338

CPC分类号： H03F3/217 ,  H03F2200/351

摘要： The integrating circuit of the triangular wave generating circuit includes an operational amplifier and a capacitor. Switch elements are alternatively turned ON and capacitors are alternatively recharged by the currents flowing in constant-current circuits thus obtaining a triangular wave on an output terminal. In this practice, when the voltage on the output terminal reaches ±1 V, comparator circuits (41, 42) and a flip-flop including NAND gates change over the switch elements. The currents flowing in the constant-current circuits are controlled depending on the current flowing in a load circuit. The current flowing in the load circuit is controlled by a PLL circuit including a phase comparator circuit, a loop filter, an LPF, an operational amplifier and an FET. This provides an output triangular wave having the same frequency as a clock pulse (CK).

摘要翻译： 三角波发生电路的积分电路包括运算放大器和电容器。 开关元件可选地导通，并且电容器由在恒流电路中流动的电流替代地再充电，从而在输出端子上获得三角波。 在这种情况下，当输出端子上的电压达到±1V时，比较器电路（41,42）和包括NAND门的触发器在开关元件上转换。 根据在负载电路中流动的电流来控制在恒流电路中流动的电流。 在负载电路中流动的电流由包括相位比较器电路，环路滤波器，LPF，运算放大器和FET的PLL电路控制。 这提供了与时钟脉冲（CK）具有相同频率的输出三角波。

公开(公告)号：US06778011B2

公开(公告)日：2004-08-17

申请号：US10207275

申请日：2002-07-29

申请人： Masao Noro ,  Nobuaki Tsuji

发明人： Masao Noro ,  Nobuaki Tsuji

IPC分类号： H03F338

CPC分类号： H03F3/2171 ,  H03F2200/03 ,  H03F2200/351

摘要： A pulse-width modulation circuit comprises a comparator having hysteresis characteristics of positive feedback, and an integrator, whose integrated output is compared with an input signal to produce a pulse-width modulation (PWM) signal having an advanced phase characteristic due to differentiation of the input signal. A switching circuit amplifies the pulse-width modulation signal based on the positive and negative source voltages (VPX, VMX). The amplified pulse-width modulation signal is supplied to a speaker via an LC filter, and it is also negatively fed back to the pulse-width modulation circuit. Since the pulse-width modulation signal whose phase is advanced is transmitted through the LC filter, it is possible to reduce phase revolution in the output of the power amplifier circuit. Thus, it is possible to effect negative feedback on the pulse-width modulation signal in a stable manner.

摘要翻译： 脉冲宽度调制电路包括具有正反馈滞后特性的比较器和积分器，其积分输出与输入信号进行比较，以产生具有先进相位特性的脉冲宽度调制（PWM）信号， 输入信号。 开关电路基于正和负电源电压（VPX，VMX）放大脉宽调制信号。 放大的脉冲宽度调制信号通过LC滤波器提供给扬声器，并且还被反馈回到脉冲宽度调制电路。 由于相位超前的脉冲宽度调制信号通过LC滤波器传输，所以可以减小功率放大器电路的输出的相位旋转。 因此，可以以稳定的方式对脉冲宽度调制信号进行负反馈。

公开(公告)号：US20090041268A1

公开(公告)日：2009-02-12

申请号：US12188835

申请日：2008-08-08

申请人： Masaya KANO ,  Hironari Kawai ,  Masao Noro

发明人： Masaya KANO ,  Hironari Kawai ,  Masao Noro

IPC分类号： H03F21/00

CPC分类号： H03F3/181 ,  H03F1/0211 ,  H03F1/0277 ,  H03F1/34 ,  H03F2200/03 ,  H03F2200/393

摘要： An amplification system of the invention can decrease power consumption in a power amplification section if the power amplification section need not be used. The power consumption in the power amplification section can be decreased by shutting off power feed into a voltage amplification stage by a power control section, and the power feed state into a power amplification stage from a power supply section is not changed. Thus, power feed into the voltage amplification stage of the circuit wherein a large current does not flow needs only to be controlled using limiter means also used for a different application, so that the power consumption of the power amplification section can be decreased without the need for enlarging the circuit scale, with saved space, and simply.

摘要翻译： 如果不需要使用功率放大部分，本发明的放大系统可以降低功率放大部分的功耗。 功率放大部分的功率消耗可以通过关闭由功率控制部分进入电压放大级的馈电来降低，并且从电源部分进入功率放大级的馈电状态不改变。 因此，不需要大电流的电路的电压放大级的馈电仅需要使用也用于不同应用的限幅器装置进行控制，从而可以在不需要的情况下降低功率放大部分的功耗 用于扩大电路规模，节省空间，简单。

公开(公告)号：US06937091B2

公开(公告)日：2005-08-30

申请号：US10632248

申请日：2003-08-01

申请人： Yasuomi Tanaka ,  Masao Noro

发明人： Yasuomi Tanaka ,  Masao Noro

IPC分类号： H03K17/687 ,  H03F3/217 ,  H03F3/30 ,  H03F3/38

CPC分类号： H03F3/2171

摘要： A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP−). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP−), to a driving circuit (304). As a result, the driving circuits (304, 305) complementarily drive power-MOS transistors (401, 402).

摘要翻译： 互补信号发生电路（301）从PWM信号产生第一互补信号（S1，S2）。 信号转换电路（302）将第一互补信号转换成具有基于负电源（VPP-）的电压分量的第二互补信号（S 3，S 4或S 5，S 6）。 在第二互补信号中，信号（S 3，S 4）被提供给驱动电路（305），并且信号（S 5，S 6）被提供给电流驱动电路（303）。 响应于信号（S 5，S 6），电流驱动电路将具有指向负电源（VPP-）的电流分量的第三互补信号（H 3，H 4）输出到驱动电路 304）。 结果，驱动电路（304,305）互补驱动功率MOS晶体管（401,402）。