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公开(公告)号：US20150058524A1
公开(公告)日：2015-02-26
申请号：US13808314
申请日：2012-01-04
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0679 , G06F13/16 , G06F13/4234 , G06F2206/1014 , G11C13/0002 , G11C14/009
摘要： Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了在相干链路和存储器扩展之间提供双模功能相关的方法和装置。 在一个实施例中，处理器经由相干互连耦合到一个或多个代理。 处理器还通过链路逻辑耦合到一个或多个双列直插式内存模块（DIMM）。 该逻辑支持基于单个数据位读取或写入指向一个或多个DIMM的命令。 还公开并要求保护其他实施例。
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公开(公告)号：US07596653B2
公开(公告)日：2009-09-29
申请号：US10984527
申请日：2004-11-08
CPC分类号： G06F13/36
摘要： A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.
摘要翻译： 一种通过点对点网络广播消息的技术。 更具体地，本发明的实施例涉及在点对点互连之间的电子部件之间广播消息。
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公开(公告)号：US08347018B2
公开(公告)日：2013-01-01
申请号：US12569772
申请日：2009-09-29
CPC分类号： G06F13/36
摘要： Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed.
摘要翻译： 描述了通过点对点网络广播消息的技术。 更具体地，本发明的一些实施例涉及在点对点互连之间的电子部件之间广播消息。 还公开了其他实施例。
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公开(公告)号：US07165131B2
公开(公告)日：2007-01-16
申请号：US10833236
申请日：2004-04-27
摘要： In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.
摘要翻译： 在本发明的一个实施例中，一种方法可以包括基于传入事务的类型，将进入的事务分离为至少第一信道，第二信道和第三信道中的相干系统的代理。 传入的事务可以由耦合到相干系统的对等设备发送。 通过基于类型分离事务，可能会避免死锁。
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5.发明授权公开(公告)号：US07996572B2
公开(公告)日：2011-08-09
申请号：US10859891
申请日：2004-06-02
申请人： Robert G. Blankenship , Robert J. Greiner , Herbert H. J. Hum , Kenneth C. Creta , Buderya S. Acharya
发明人： Robert G. Blankenship , Robert J. Greiner , Herbert H. J. Hum , Kenneth C. Creta , Buderya S. Acharya
CPC分类号： G06F13/387 , G06Q10/087
摘要： Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.
摘要翻译： 管理事务的系统和方法提供在第一I / O集线器处接收第一冲洗命令，其中第一冲洗命令专用于未发布的事务。 一个实施例进一步提供响应于第一冲洗命令而停止关于非发布的事务的第一I / O集线器的入站订购队列，并将未发布的事务从第一I / O集线器的输出缓冲器刷新到 第二个I / O中枢，而对于未发布的事务，入站订购队列被停止。
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6.发明授权Providing common caching agent for core and integrated input/output (IO) module 有权为核心和集成输入/输出（IO）模块提供通用缓存代理公开(公告)号：US08984228B2
公开(公告)日：2015-03-17
申请号：US13324053
申请日：2011-12-13
申请人： Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
发明人： Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
CPC分类号： G06F12/084 , G06F12/0815 , G06F12/0831 , G06F2212/452 , G06F2212/621 , Y02D10/13
摘要： In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。
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公开(公告)号：US08046539B2
公开(公告)日：2011-10-25
申请号：US12479541
申请日：2009-06-05
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译： 一种用于同步分布式缓存的方法和装置。 更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。
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公开(公告)号：US20090240894A1
公开(公告)日：2009-09-24
申请号：US12479541
申请日：2009-06-05
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译： 一种用于同步分布式缓存的方法和装置。 更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。
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公开(公告)号：US20130151782A1
公开(公告)日：2013-06-13
申请号：US13324053
申请日：2011-12-13
申请人： Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
发明人： Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0815 , G06F12/0831 , G06F2212/452 , G06F2212/621 , Y02D10/13
摘要： In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.
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公开(公告)号：US20100017458A1
公开(公告)日：2010-01-21
申请号：US12569772
申请日：2009-09-29
IPC分类号： G06F15/16
CPC分类号： G06F13/36
摘要： Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed.
摘要翻译： 描述了通过点对点网络广播消息的技术。 更具体地，本发明的一些实施例涉及在点对点互连之间的电子部件之间广播消息。 还公开了其他实施例。
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