公开(公告)号：US08984228B2

公开(公告)日：2015-03-17

申请号：US13324053

申请日：2011-12-13

申请人： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

发明人： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

摘要： In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。

公开(公告)号：US08751714B2

公开(公告)日：2014-06-10

申请号：US12889777

申请日：2010-09-24

申请人： Robert J. Safranek ,  Debendra Das Sharma ,  Ganapati N. Srinivasa

发明人： Robert J. Safranek ,  Debendra Das Sharma ,  Ganapati N. Srinivasa

IPC分类号： G06F13/42

CPC分类号： G06F12/0835

摘要： Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry.

摘要翻译： 通过PCIe接口实现Intel QuickPathInterconnect®（QPI）协议的方法和设备。 通过使用QPI数据位映射到相应的PCIe x16，x8和x4通道配置，QPI协议的上层通过PCIe接口的物理层实现。 采用QPI链路层到PCIe物理层接口从底层PCIe物理层（和相应的PCIe接口电路）抽取QPI链路，路由和协议层，从而使QPI协议消息能够在PCIe硬件上采用。 因此，诸如支持相干存储器事务的QPI功能可以通过PCIe接口电路来实现。

公开(公告)号：US20140281457A1

公开(公告)日：2014-09-18

申请号：US13854001

申请日：2013-03-29

申请人： Elierzer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

发明人： Elierzer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC分类号： G06F9/44

CPC分类号： G06F9/4401 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

摘要翻译： 描述异构处理器架构和启动异构处理器的方法。 根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。 引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

公开(公告)号：US20140189704A1

公开(公告)日：2014-07-03

申请号：US13730539

申请日：2012-12-28

申请人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

发明人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC分类号： G06F9/50

CPC分类号： G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

摘要翻译： 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心组内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：US20140189377A1

公开(公告)日：2014-07-03

申请号：US13730493

申请日：2012-12-28

申请人： Dheeraj R. Subbareddy ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Scott D. Hahn ,  David A. Koufaty ,  Paul Brett ,  Abirami Prabhakaran

发明人： Dheeraj R. Subbareddy ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Scott D. Hahn ,  David A. Koufaty ,  Paul Brett ,  Abirami Prabhakaran

IPC分类号： G06F1/26

CPC分类号： G06F9/44 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  G09G5/363 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/24

摘要： An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

摘要翻译： 用于处理器的智能功率分配架构。 例如，处理器的一个实施例包括：用于执行相应的多个处理器功能的多个处理器组件; 多个电力平面，与所述处理器组件中的一个相关联的每个电力平面; 以及功率控制单元（PCU），用于基于用于当前使用处理器的用户体验度量，工作负载特性和功率约束来动态地调整每个功率平面的功率。

公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/10

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20140298140A1

公开(公告)日：2014-10-02

申请号：US13994105

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Oded Lempel ,  Hisham Hafi ,  Geeyarpuram N Santhanakrisnan ,  Jose A Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Yuli Mandelblat

发明人： Theodros Yigzaw ,  Oded Lempel ,  Hisham Hafi ,  Geeyarpuram N Santhanakrisnan ,  Jose A Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Yuli Mandelblat

IPC分类号： G06F11/10

CPC分类号： G06F11/1064 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1407

摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

摘要翻译： 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令获取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

公开(公告)号：US20120079156A1

公开(公告)日：2012-03-29

申请号：US12889777

申请日：2010-09-24

申请人： Robert J. Safranek ,  Debendra Das Sharma ,  Ganapati N. Srinivasa

发明人： Robert J. Safranek ,  Debendra Das Sharma ,  Ganapati N. Srinivasa

IPC分类号： G06F13/40 ,  G06F12/08

CPC分类号： G06F12/0835

摘要： Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry.

摘要翻译： 通过PCIe接口实现Intel QuickPathInterconnect®（QPI）协议的方法和设备。 通过使用QPI数据位映射到相应的PCIe x16，x8和x4通道配置，QPI协议的上层通过PCIe接口的物理层实现。 采用QPI链路层到PCIe物理层接口从底层PCIe物理层（和相应的PCIe接口电路）抽取QPI链路，路由和协议层，从而使QPI协议消息能够在PCIe硬件上采用。 因此，诸如支持相干存储器事务的QPI功能可以通过PCIe接口电路来实现。

公开(公告)号：US09639490B2

公开(公告)日：2017-05-02

申请号：US13994792

申请日：2011-11-29

申请人： Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Yen-Cheng Liu ,  Bahaa Fahim ,  Ganapati N. Srinivasa

发明人： Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Yen-Cheng Liu ,  Bahaa Fahim ,  Ganapati N. Srinivasa

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F17/13 ,  G06F17/50

CPC分类号： G06F13/4022 ,  G06F13/1668 ,  G06F13/4247 ,  G06F13/4291 ,  G06F17/13 ,  G06F17/5036

摘要： Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

公开(公告)号：US20150269104A1

公开(公告)日：2015-09-24

申请号：US13994792

申请日：2011-11-29

申请人： Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Yen-Cheng Liu ,  Bahaa Fahim ,  Ganapati N. Srinivasa

发明人： Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Yen-Cheng Liu ,  Bahaa Fahim ,  Ganapati N. Srinivasa

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/1668 ,  G06F13/4247 ,  G06F13/4291 ,  G06F17/13 ,  G06F17/5036

摘要： Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

摘要翻译： 用于在CPU和相关协议之间实现低延迟互连交换机的方法，系统和设备。 CPU被配置为安装在主板上，包括通过CPU插座到插座互连链路链接在一起的多个CPU插槽，形成CPU插座到插座环互连。 CPU也配置为通过CPU插座到插座互连发送数据来相互传输数据。 可以使用诸如QPI的分组协议来传送数据，并且CPU还可以被配置为支持跨CPU的相干存储器事务。