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    METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES
    1.
    发明申请
    METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES 审中-公开
    增加可编程逻辑器件制造工艺的方法

    公开(公告)号：US20100333058A1

    公开(公告)日：2010-12-30

    申请号：US12875517

    申请日：2010-09-03

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

    摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

    摘要翻译： 一种提高现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

    Method for increasing the manufacturing yield of programmable logic devices
    2.
    发明授权
    Method for increasing the manufacturing yield of programmable logic devices 失效
    提高可编程逻辑器件制造产量的方法

    公开(公告)号：US07793251B2

    公开(公告)日：2010-09-07

    申请号：US11275536

    申请日：2006-01-12

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

    摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

    摘要翻译： 一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

    Processor pipeline architecture logic state retention systems and methods
    3.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07937560B2

    公开(公告)日：2011-05-03

    申请号：US12121292

    申请日：2008-05-15

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

    摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

    System and Method for Dynamically Executing a Function in a Programmable Logic Array
    4.
    发明申请
    System and Method for Dynamically Executing a Function in a Programmable Logic Array 失效
    用于在可编程逻辑阵列中动态执行功能的系统和方法

    公开(公告)号：US20080290896A1

    公开(公告)日：2008-11-27

    申请号：US12185467

    申请日：2008-08-04

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

    摘要： A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

    摘要翻译： 可重构逻辑阵列（RLA）系统，其包括RLA和用于在循环基础上重新编程RLA的编程器。 需要比RLA中包含的逻辑量​​大的函数（F）被划分为多个功能块。 程序员包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

    System and method for dynamically executing a function in a programmable logic array
    6.
    发明授权
    System and method for dynamically executing a function in a programmable logic array 失效
    用于在可编程逻辑阵列中动态执行功能的系统和方法

    公开(公告)号：US06954085B2

    公开(公告)日：2005-10-11

    申请号：US10605603

    申请日：2003-10-13

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    IPC分类号： G06F15/78 ,  H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

    摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

    摘要翻译： 一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。 需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。 程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当程序员使用下一个功能块重新配置功能区域并且重新配置用于接收下一个功能块的输出的一个存储区域时，从当前功能块传递到下一个功能块的数据被保存在 其他存储区域。

    FPGA powerup to known functional state
    7.
    发明授权
    FPGA powerup to known functional state 失效
    FPGA上电到已知的功能状态

    公开(公告)号：US07489163B2

    公开(公告)日：2009-02-10

    申请号：US11869921

    申请日：2007-10-10

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

    摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

    摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

    Processor pipeline architecture logic state retention systems and methods
    8.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07882334B2

    公开(公告)日：2011-02-01

    申请号：US11276236

    申请日：2006-02-20

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3869 ,  G11C27/026

    摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

    System and method for dynamically executing a function in a programmable logic array
    9.
    发明授权
    System and method for dynamically executing a function in a programmable logic array 失效
    用于在可编程逻辑阵列中动态执行功能的系统和方法

    公开(公告)号：US07750670B2

    公开(公告)日：2010-07-06

    申请号：US12185467

    申请日：2008-08-04

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

    摘要： A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.

    摘要翻译： 具有逻辑容量并被配置为处理具有超过RLA的逻辑容量的总逻辑要求的功能的可重构逻辑阵列（RLA）。 RLA包括第一和第二存储区域以及位于第一和第二存储区域之间的多个可编程逻辑元件。 当功能被解析成多个功能块时，该配置允许RLA通过在RLA内沿交替方向依次处理功能块来处理功能，使用多个可编程逻辑元件来顺序地处理每个功能块和 使用第一和第二存储区域临时保持该功能块的输入和输出。