公开(公告)号：US07307222B2

公开(公告)日：2007-12-11

申请号：US10670649

申请日：2003-09-24

申请人： Kenneth P. Parker ,  Ronald J. Peiffer ,  Glen E. Leinbach

发明人： Kenneth P. Parker ,  Ronald J. Peiffer ,  Glen E. Leinbach

IPC分类号： H01R12/04 ,  H05K1/11 ,  G01R31/02

CPC分类号： H05K1/0268 ,  G01R31/2805 ,  G01R31/2818 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0989 ,  H05K2203/043

摘要： A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. In an x-, y-, z-coordinate system where traces are printed along an x-y plane, the z-dimension is used to implement test access point structures. Each test access point structure is conductively connected to a trace at a test access point directly on top of the trace and along the z axis of the x-, y-, z-coordinate system above an exposed surface of the printed circuit board to be accessible for electrical probing by an external device.

摘要翻译： 介绍了一种用于访问印刷电路板测试点的测试接入点结构及其制造方法。 在沿x-y平面打印痕迹的x，y，z坐标系中，z维用于实现测试接入点结构。 每个测试接入点结构在测试接入点处直接连接到轨迹顶部的迹线上，并且沿x，y，z坐标系的z轴在印刷电路板的暴露表面上导电连接为 可通过外部设备进行电气探测。

公开(公告)号：US5760596A

公开(公告)日：1998-06-02

申请号：US810202

申请日：1997-03-03

申请人： Ronald J. Peiffer ,  Kenneth P. Parker

发明人： Ronald J. Peiffer ,  Kenneth P. Parker

IPC分类号： G01R31/02 ,  G01R27/08

CPC分类号： G01R31/02

摘要： A method of testing series passive components in electronic assemblies. Only one test pin per passive component is required, thereby reducing the cost and complexity of test fixtures and the electronic assemblies. A passive component is connected between the output of a driving circuit and (optionally) an input of a receiving circuit. The output of the driving circuit is placed in a low impedance state. The receiving end of the passive component is stimulated and the response is measured. For reactive components, the stimulus and response are AC. For resistors, multiple DC measurements may be made. A optional DC bias may be provided to limit DC current and to further reduce the small signal output impedance of the driving circuit.

摘要翻译： 一种在电子组件中测试串联无源元件的方法。 每个被动元件只需要一个测试针，从而降低测试夹具和电子组件的成本和复杂性。 无源元件连接在驱动电路的输出端和（可选地）接收电路的输入端之间。 驱动电路的输出处于低阻态。 对被动元件的接收端进行刺激并测量响应。 对于反应性组分，刺激和反应是AC。 对于电阻器，可以进行多个直流测量。 可以提供可选的直流偏压来限制直流电流并进一步降低驱动电路的小信号输出阻抗。

公开(公告)号：US20080315892A1

公开(公告)日：2008-12-25

申请号：US12011884

申请日：2008-01-30

申请人： Kenneth P. Parker ,  Chris Richard Jacobsen

发明人： Kenneth P. Parker ,  Chris Richard Jacobsen

IPC分类号： G01R31/04

CPC分类号： G01R31/2812

摘要： A method of testing for shorts between nodes of a circuit assembly includes parsing circuit design data to identify positional data for nodes of a circuit assembly, and using the positional data to classify ones of the nodes as members of a supernode, where each member of the supernode is unlikely to be shorted to any other member of the supernode. Tests for shorts in a set of nodes that includes the supernode and a plurality of other nodes of the circuit assembly are then conducted, by iteratively i) stimulating a particular one of the set of nodes, and ii) while stimulating the particular node, grounding at least one other node in the set of nodes and monitoring a current flow through the particular node. When stimulating or grounding a supernode, all of the nodes that are members of the supernode are stimulated or grounded. If a current flow is detected through one of the stimulated nodes, the circuit assembly is indicated to be defective. Other embodiments are also disclosed.

摘要翻译： 测试电路组件的节点之间的短路的方法包括解析电路设计数据以识别电路组件的节点的位置数据，并且使用位置数据将节点中的一个分类为超级节点的成员，其中每个成员 超级节点不可能与超级节点的任何其他成员短路。 然后，通过迭代地i）刺激该组节点中的特定节点，以及ii）在刺激该特定节点的同时，对该节点的包含超级节点和多个其他节点的节点进行短路测试 在该组节点中的至少一个其他节点并且监视通过特定节点的当前流。 当刺激或接地超级节点时，作为超级节点成员的所有节点都被刺激或接地。 如果通过刺激节点之一检测到电流，则电路组件被指示为有缺陷的。 还公开了其他实施例。

公开(公告)号：US07190157B2

公开(公告)日：2007-03-13

申请号：US10972822

申请日：2004-10-25

申请人： Kenneth P. Parker

发明人： Kenneth P. Parker

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2818 ,  G01R31/281

摘要： A layout independent test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to various locations along a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe.

摘要翻译： 提出了一种用于访问印刷电路板测试点的布局独立测试接入点结构及其制造方法。 每个测试接入点结构沿着测试接入点处的迹线和印刷电路板的暴露表面上方的导电性连接到可访问的夹具探针探测的各个位置。

公开(公告)号：US07123022B2

公开(公告)日：2006-10-17

申请号：US10836862

申请日：2004-04-28

申请人： Kenneth P. Parker ,  Chris R. Jacobsen ,  Myron J. Schneider

发明人： Kenneth P. Parker ,  Chris R. Jacobsen ,  Myron J. Schneider

IPC分类号： G01R31/02

CPC分类号： G01R31/312 ,  G01R31/026 ,  G01R31/046

摘要： A device for enabling testing of electrical paths through a circuit assembly is presented. The device may include a non-contact connector test probe for a testing a connector of the circuit assembly. A method for testing continuity of electrical paths through a circuit assembly is presented. In the method, one or more nodes of the circuit assembly are stimulated, connector pins of a connector on the circuit assembly are capacitively coupled to a non-contact connector test probe, and an electrical characteristic is measured by a tester coupled to the non-contact connector test probe to determine continuity of electrical paths through the circuit assembly.

摘要翻译： 提出了一种能够通过电路组件测试电气路径的装置。 该装置可以包括用于测试电路组件的连接器的非接触式连接器测试探头。 提出了一种用于测试通过电路组件的电气路径的连续性的方法。 在该方法中，电路组件的一个或多个节点被激励，电路组件上的连接器的连接器引脚电容耦合到非接触式连接器测试探针，并且电特性由耦合到非接触式连接器的测试仪测量， 接触连接器测试探头，以确定通过电路组件的电气路径的连续性。

公开(公告)号：US07068039B2

公开(公告)日：2006-06-27

申请号：US10834449

申请日：2004-04-28

申请人： Kenneth P. Parker

发明人： Kenneth P. Parker

IPC分类号： G01R31/28

CPC分类号： G01R31/312 ,  G01R31/046

摘要： A device for enabling testing of electrical paths through a circuit assembly is presented. The device may include a test facilitating shipping and handling cover for a socket of the circuit assembly. The test facilitating shipping and handling cover may have a conductive layer for capacitively coupling to an array of pins in the socket during testing. A method for testing continuity of electrical paths through a circuit assembly is presented. In the method, one or more nodes of the circuit assembly are stimulated, contacts of a socket on the circuit assembly are capacitively coupled with a conductive layer of a shipping and handling cover mated with the socket, and an electrical characteristic is measured by a tester coupled to the shipping and handling cover to determine continuity of electrical paths through the circuit assembly.

摘要翻译： 提出了一种能够通过电路组件测试电气路径的装置。 该装置可以包括促进电路组件的插座的运输和处理盖的测试。 便于运输和处理盖的测试可以具有用于在测试期间电容耦合到插座中的销的阵列的导电层。 提出了一种用于测试通过电路组件的电气路径的连续性的方法。 在该方法中，电路组件的一个或多个节点被刺激，电路组件上的插座的触点与与插座配合的运输和处理盖的导电层电容耦合，电特性由测试仪测量 耦合到运输和处理盖以确定通过电路组件的电路径的连续性。

公开(公告)号：US07325219B2

公开(公告)日：2008-01-29

申请号：US11058811

申请日：2005-02-16

申请人： Chris R. Jacobsen ,  Kenneth P. Parker

发明人： Chris R. Jacobsen ,  Kenneth P. Parker

IPC分类号： G06F17/50

CPC分类号： G01R31/2801

摘要： Techniques for automating probing location selection during printed circuit board (PCB) and corresponding PCB tester fixture design are presented. The invention includes a system and algorithm for selecting a probe layout comprising a set of probing locations for a printed circuit board design having a plurality of nets, at least some of which have a number of alternative possible probing locations. The system and algorithm iteratively generates a potential probe layout comprising one or more probing locations per net, and based on the potential probe layout, determines one or more regions of maximum deflection. A probing location from the potential probe layout that is located in a region of maximum deflection and is associated with a net having one or more alternative probing locations is removed from the potential probe layout and replaced in the with one of the one or more alternate probing locations associated with the net. Regions of maximum deflection are recalculated based on the modified potential probe layout, and the replacement process is repeated until respective magnitudes of the respective areas of maximum deflection are below a threshold value.

摘要翻译： 介绍了印刷电路板（PCB）和对应的PCB测试仪器设计中自动化探测位置选择的技术。 本发明包括用于选择探针布局的系统和算法，其包括用于具有多个网络的印刷电路板设计的一组探测位置，其中至少一些网络具有多个替代可能的探测位置。 系统和算法迭代地生成包括每个网络的一个或多个探测位置的潜在探测器布局，并且基于潜在的探测器布局来确定最大偏转的一个或多个区域。 来自位于最大偏转区域并与具有一个或多个替代探测位置的网络相关联的潜在探针布局的探测位置从潜在探针布局中移除并且用一个或多个替代探测中的一个替换 与网络相关的位置。 基于经修改的电位探针布局重新计算最大偏转区域，并重复替换处理，直到各个最大偏转区域的大小低于阈值。

公开(公告)号：US07307427B2

公开(公告)日：2007-12-11

申请号：US11188080

申请日：2005-07-23

申请人： Chris R. Jacobsen ,  Kenneth P. Parker ,  Myron J. Schneider ,  Tak Yee Kwan

发明人： Chris R. Jacobsen ,  Kenneth P. Parker ,  Myron J. Schneider ,  Tak Yee Kwan

IPC分类号： G01R31/08

CPC分类号： G01R31/2853 ,  G01R1/0433 ,  G01R31/312

摘要： A method and apparatus is presented for gaining socket testability through the use of a capacitive interposer engineered to create capacitive coupling between signal nodes of a circuit assembly that the tester has access to and nodes of the socket that would not otherwise have any coupling to a testable signal node of the socket. Generally, coupling capacitance is engineered into the interposer by trace and via routing between the signal node of the socket and a location in close proximity to the inaccessible socket node such that their proximity to each other couples them together.

摘要翻译： 提出了一种方法和装置，通过使用设计用于在测试器可访问的电路组件的信号节点与插座的节点之间建立电容耦合的电容性插入器来获得插座可测试性，否则该插座的节点将不具有与可测试的任何耦合 信号节点的插座。 通常，耦合电容通过插座的信号节点和紧邻不可访问的插座节点的位置之间的跟踪和通路布线被设计到插入器中，使得它们彼此的接近度将它们耦合在一起。

公开(公告)号：US07295031B1

公开(公告)日：2007-11-13

申请号：US11484952

申请日：2006-07-12

申请人： Kenneth P. Parker ,  Chris R. Jacobsen ,  Dayton Norrgard ,  Myron J. Schneider

发明人： Kenneth P. Parker ,  Chris R. Jacobsen ,  Dayton Norrgard ,  Myron J. Schneider

IPC分类号： G01R31/26 ,  G01R31/04

CPC分类号： G01R31/046

摘要： Non-contact connectivity testing of joints connecting circuit junctions are improved through knowledge of characteristics of semiconductor junctions connected to component nodes of components of a device under test (DUT) to allow detection of high-impedance joints.

摘要翻译： 通过了解连接到被测设备（DUT）的组件的元件节点的半导体结的特性，从而提高了连接电路结的接头的非接触连接性测试，以便检测高阻抗接头。

公开(公告)号：US07224169B2

公开(公告)日：2007-05-29

申请号：US10979590

申请日：2004-11-02

申请人： Kenneth P. Parker

发明人： Kenneth P. Parker

IPC分类号： G01R31/08 ,  G01R27/26

CPC分类号： G01R31/312

摘要： A method and apparatus for detecting shorts between accessible and inaccessible signal nodes (e.g., integrated circuit pins) of an electrical device (e.g., an integrated circuit), using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible node under test is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to at least one of the accessible node and inaccessible node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a signal present on the at least one of the accessible node and inaccessible node of the electrical device. Based on the value of the capacitively sensed signal, a known expected “defect-free” capacitively sensed signal measurement and/or a known expected “shorted” capacitively sensed signal measurement, one can determine whether a short fault exists between the accessible node and inaccessible node of the electrical device.

摘要翻译： 提出了一种使用电容引线框技术来检测电气设备（例如，集成电路）的可访问和不可访问的信号节点（例如，集成电路引脚）之间的短路的方法和装置。 根据本发明的方法，用已知的源信号刺激被测的可访问节点。 电容感测板电容耦合到电气设备的可访问节点和不可访问节点中的至少一个，并且耦合到电容检测板的测量设备电容性地感测存在于可访问节点和不可访问节点的至少一个上的信号 的电气设备。 基于电容感测信号的值，已知的预期的“无缺陷”电容式感测信号测量和/或已知的预期“短路”电容式感测信号测量，可以确定在可访问节点和不可访问的节点之间是否存在短路故障 节点的电气设备。