公开(公告)号：US07987158B2

公开(公告)日：2011-07-26

申请号：US11054976

申请日：2005-02-09

申请人： Kenneth Wayne Boyd ,  Kenneth Fairclough Day, III ,  Mark Edward Dean ,  John Jay Wolfgang

发明人： Kenneth Wayne Boyd ,  Kenneth Fairclough Day, III ,  Mark Edward Dean ,  John Jay Wolfgang

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： G06F11/2097 ,  G06F11/1662 ,  G06F11/2064 ,  G06F11/2071

摘要： Data and metadata are generated in a computational device, wherein the generated data is stored in a first physical storage device coupled to the computational device, and wherein the generated metadata is stored transiently in the computational device. The data and the metadata are replicated to a second physical storage device. The replicated data and the replicated metadata in the second physical storage device are used to recover from a failure of at least one of the computational device and the first physical storage device.

摘要翻译： 在计算设备中生成数据和元数据，其中生成的数据被存储在耦合到计算设备的第一物理存储设备中，并且其中生成的元数据被暂时存储在计算设备中。 数据和元数据被复制到第二物理存储设备。 第二物理存储设备中的复制数据和复制的元数据用于从计算设备和第一物理存储设备中的至少一个的故障中恢复。

公开(公告)号：US06269428B1

公开(公告)日：2001-07-31

申请号：US09259367

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F12/0813

摘要： A method for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request by a processor of a first node to invalidate a remote copy of a cache line also stored within its cache memory at substantially the same time when a processor of a second node is also requesting to invalidate said cache line, one of the two requests is allowed to complete. The allowed request is the first request to complete without retry at the point of coherency, typically the home node. Subsequently, the other one of the two requests is permitted to complete.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问系统内的无效事务的冲突而导致的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于第一节点的处理器在第二节点的处理器也要求使所述高速缓存行无效的基本上同时存储在其高速缓冲存储器中的高速缓存行的远端副本的请求时， 这两个请求被允许完成。 允许的请求是第一个完成的请求，而不是在一致性的时候重试，通常是家庭节点。 随后，两个请求中的另一个被允许完成。

公开(公告)号：US6148361A

公开(公告)日：2000-11-14

申请号：US213998

申请日：1998-12-17

申请人： Gary Dale Carpenter ,  Philippe Louis deBacker ,  Mark Edward Dean ,  David Brian Glasco ,  Ronald Lynn Rockhold

发明人： Gary Dale Carpenter ,  Philippe Louis deBacker ,  Mark Edward Dean ,  David Brian Glasco ,  Ronald Lynn Rockhold

IPC分类号： G06F15/173 ,  G06F9/48 ,  G06F13/24

CPC分类号： G06F9/4812

摘要： A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统包括由节点互连耦合的至少两个节点，其中至少一个节点包括用于维护中断的处理器。 节点被划分为外部中断域，以便外部中断始终呈现给发生中断的外部中断域内的处理器。 虽然每个外部中断域通常仅包括一个节点，但是可以实现中断通道或中断漏斗，以跨越节点边界路由外部中断以呈现给处理器。 一旦提交给处理器，中断处理软件就可以在任何处理器上执行以服务外部中断。 与现有技术的方法相比，通过减小中断处理程序轮询链的大小来加快服务外部中断。 除了外部中断之外，本发明的中断架构还支持处理器间中断（IPI），通过该处理器中断，任何处理器可以中断自身或NUMA计算机系统中的一个或多个其他处理器。 通过写入全局系统存储器中的存储器映射寄存器来触发IPI，这有助于跨越节点边界的IPI的传输，并且允许通过向包含待中断的处理器的每个节点发送一个写入事务来简单地触发多播IPI。 每个节点中的中断硬件也被分配用于可扩展性，硬件组件通过跨共享通信路径传送的中断事务进行通信。

公开(公告)号：US6067611A

公开(公告)日：2000-05-23

申请号：US106945

申请日：1998-06-30

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta

IPC分类号： G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F15/16

CPC分类号： G06F15/17

摘要： A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

摘要翻译： 不均匀存储器访问（NUMA）计算机系统包括多个处理节点（包括第一，第二和第三处理节点）耦合到的互连。 第一，第二和第三处理节点中的每一个包括至少一个处理器和本地系统存储器。 NUMA计算机系统还包括耦合到互连的事务缓冲器，其存储在互连上发送的通信事务，所述通信事务由第三处理节点以外的处理节点发起和定向。 响应于原先针对另一个处理节点的特定通信交易应该由第三处理节点处理的响应，耦合到事务缓冲器的缓冲器控制逻辑使得从事务缓冲器检索特定的通信事务并且通过第三处理进行处理 节点。 在一个实施例中，互连包括广播结构，并且事务缓冲器和缓冲器控制逻辑形成第三处理节点的一部分。

公开(公告)号：US6067603A

公开(公告)日：2000-05-23

申请号：US165177

申请日：1998-10-01

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F2212/2542 ,  G06F2212/507

摘要： A computer system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect, where each such request transaction specifies an associated datum. The node controller of the second processing node handles each speculatively transmitted request transaction received in response to a directory state of its associated datum.

摘要翻译： 计算机系统包括至少第一处理节点和第二处理节点耦合到的节点互连。 第一处理节点和第二处理节点各自包括本地互连，耦合到本地互连的处理器，耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。 为了减少通信等待时间，第一处理节点的节点控制器通过节点互连，将从第一处理节点的本地互连接收的请求事务推测地发送到第二处理节点，其中每个这样的请求事务指定相关联的数据。 第二处理节点的节点控制器处理响应于其相关联的数据的目录状态而接收的每个推测发送的请求事务。

公开(公告)号：US06763474B1

公开(公告)日：2004-07-13

申请号：US09631712

申请日：2000-08-03

申请人： David William Boerstler ,  Mark Edward Dean ,  Hung Cai Ngo ,  Andrew Christian Zimmerman

发明人： David William Boerstler ,  Mark Edward Dean ,  Hung Cai Ngo ,  Andrew Christian Zimmerman

IPC分类号： G06P112

CPC分类号： H03L7/23

摘要： An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.

摘要翻译： 用于节点同步的装置和方法，其可以用于系统中的节点不共享公共系统时钟的异构计算机系统中。 重要的时间戳附加在交易请求上。 时间戳基于“时间”值，其可以简单地是由系统时钟增加的寄存器。 由于每个节点都有自己的系统时钟，这些时钟的频率可能会偏移，这会导致时间戳值的变化。 如果值漂移太远，数据更新可能会丢失。 能够将高分辨率和快速频率调节的频率合成器连接到系统时钟。 当检测到主从时间之间的相位偏移时，可以将频率合成器输出改变少量以使两个信号回到相位。

公开(公告)号：US06338122B1

公开(公告)日：2002-01-08

申请号：US09211351

申请日：1998-12-15

申请人： Yoanna Baumgartner ,  Mark Edward Dean ,  Anna Elman

发明人： Yoanna Baumgartner ,  Mark Edward Dean ,  Anna Elman

IPC分类号： G06F1200

CPC分类号： G06F12/0815 ,  G06F12/0817 ,  G06F2212/507

摘要： A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统至少包括本地处理节点和每个耦合到节点互连的远程处理节点。 本地处理节点包括本地互连，处理器和耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。 响应于从本地互连接收到读请求，节点控制器通过节点互连器向远程处理节点推测性地发送读请求。 此后，响应于从远程处理节点接收到对读取请求的响应，节点控制器根据本地处理节点处的读取请求的分辨率处理响应。 例如，在一个处理场景中，如果读请求在本地处理节点处接收到修改的干预一致性响应，节点控制器将丢弃从远程处理节点接收到的响应中包含的数据。

公开(公告)号：US06334177B1

公开(公告)日：2001-12-25

申请号：US09216223

申请日：1998-12-18

申请人： Yoanna Baumgartner ,  Alvaro Eduardo Benavides ,  Mark Edward Dean ,  John Thomas Hollaway, Jr.

发明人： Yoanna Baumgartner ,  Alvaro Eduardo Benavides ,  Mark Edward Dean ,  John Thomas Hollaway, Jr.

IPC分类号： G06F1314

CPC分类号： G06F9/5077 ,  G06F12/0817 ,  G06F2212/2542

摘要： A method for supporting software partition and dynamic reconfiguration within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes multiple nodes coupled to an interconnect. Each of the nodes includes a NUMA bridge, a local system memory, and at least one processor having at least a local cache memory. Multiple groups of software partitions are formed within the NUMA computer system, and each of the software partitions is formed by a subset of the nodes. A destination map table is provided in a NUMA bridge of each of the nodes for keeping track of the nodes within a software partition. A command is forwarded to only the nodes within a software partition.

摘要翻译： 公开了一种在非均匀存储器访问（NUMA）计算机系统内支持软件分区和动态重新配置的方法。 NUMA计算机系统包括耦合到互连的多个节点。 每个节点包括NUMA桥，本地系统存储器和至少一个具有至少一个本地高速缓冲存储器的处理器。 在NUMA计算机系统内形成多组软件分区，并且每个软件分区由节点的子集形成。 在每个节点的NUMA桥中提供目的地地图表，用于跟踪软件分区内的节点。 命令只转发到软件分区中的节点。

公开(公告)号：US06192452B1

公开(公告)日：2001-02-20

申请号：US09259378

申请日：1999-02-26

申请人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： A method for avoiding data loss due to cancelled transactions within a non-uniform memory access (NUMA) data processing system is disclosed. A NUMA data processing system includes a node interconnect to which at least a first node and a second node are coupled. The first and the second nodes each includes a local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and a node interconnect. The node controller detects certain situations which, due to the nature of a NUMA data processing system, can lead to data loss. These situations share the common feature that a node controller ends up with the only copy of a modified cache line and the original transaction that requested the modified cache line may not be issued again with the same tag or may not be issued again at all. The node controller corrects these situations by issuing its own write transaction to the system memory for that modified cache line using its own tag, and then providing the data the modified cache line is holding. This ensures that the modified data will be written to the system memory.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问（NUMA）数据处理系统中被取消的事务而导致的数据丢失的方法。 NUMA数据处理系统包括至少第一节点和第二节点耦合到的节点互连。 第一和第二节点各自包括本地互连，耦合到本地互连的系统存储器和插入在本地互连和节点互连之间的节点控制器。 节点控制器检测某些情况，由于NUMA数据处理系统的性质，可能导致数据丢失。 这些情况共享了节点控制器以修改的高速缓存行的唯一副本结束的共同特征，并且请求修改的高速缓存行的原始事务可能不会以相同的标签重新发出，也可能根本不再发出。 节点控制器通过使用其自己的标签向修改的高速缓存行发出自己的写入事务来修正这些情况，然后提供修改后的高速缓存行正在保存的数据。 这样可以确保将修改后的数据写入系统内存。

公开(公告)号：US06566921B1

公开(公告)日：2003-05-20

申请号：US09631718

申请日：2000-08-03

申请人： David William Boerstler ,  Mark Edward Dean ,  Hung Cai Ngo ,  Andrew Christian Zimmerman

发明人： David William Boerstler ,  Mark Edward Dean ,  Hung Cai Ngo ,  Andrew Christian Zimmerman

IPC分类号： H03L706

CPC分类号： H03L7/23

摘要： An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.

摘要翻译： 一种用于在多级频率合成器中进行高分辨率频率调整的装置和方法。 频率合成器的初始阶段是连接到动态可变分频器的常规锁相环。 存在一个或多个中间级，其包括通过固定分频器反馈并连接到动态可变分频器的锁相环的前部。 最后一个阶段包括通过固定分频器反馈并连接到另一个固定分频器的锁相环的前向部分。 通过改变电路中可变分频器的分频常数，可以非常快速地进行微调频率调整。 调整精度取决于分频器的相对值和系统中的中间级数。