公开(公告)号：US11765908B1

公开(公告)日：2023-09-19

申请号：US18167816

申请日：2023-02-10

申请人： Kepler Computing Inc.

发明人： Mauricio Manfrini ,  Noriyuki Sato ,  James David Clarkson ,  Abel Fernandez ,  Somilkumar J. Rathi ,  Niloy Mukherjee ,  Tanay Gosavi ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

公开(公告)号：US20240276735A1

公开(公告)日：2024-08-15

申请号：US18448918

申请日：2023-08-12

申请人： Kepler Computing Inc.

发明人： Biswajeet Guha ,  Mauricio Manfrini ,  Noriyuki Sato ,  James David Clarkson ,  Abel Fernandez ,  Somilkumar J. Rathi ,  Niloy Mukherjee ,  Tanay Gosavi ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H10B53/30 ,  H01L23/00

CPC分类号： H10B53/30 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/80931 ,  H01L2924/04941 ,  H01L2924/04953

摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

公开(公告)号：US20240276734A1

公开(公告)日：2024-08-15

申请号：US18448917

申请日：2023-08-12

申请人： Kepler Computing Inc.

发明人： Biswajeet Guha ,  Mauricio Manfrini ,  Noriyuki Sato ,  James David Clarkson ,  Abel Fernandez ,  Somilkumar J. Rathi ,  Niloy Mukherjee ,  Tanay Gosavi ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20

CPC分类号： H10B53/20 ,  H01L28/55 ,  H01L28/91 ,  H01L28/92 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/20

摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

公开(公告)号：US20240274651A1

公开(公告)日：2024-08-15

申请号：US18448852

申请日：2023-08-11

申请人： Kepler Computing Inc.

发明人： Biswajeet Guha ,  Mauricio Manfrini ,  Noriyuki Sato ,  James David Clarkson ,  Abel Fernandez ,  Somilkumar J. Rathi ,  Niloy Mukherjee ,  Tanay Gosavi ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H10N52/00 ,  H01L23/00

CPC分类号： H01L28/60 ,  H01L24/32 ,  H01L28/55 ,  H01L2224/32145

摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.