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公开(公告)号：US11894417B2
公开(公告)日：2024-02-06
申请号：US17649899
申请日：2022-02-03
Applicant: Kepler Computing Inc.
Inventor： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC: H01L21/768 , H01L21/324 , H10B53/30 , H10N70/20 , H10N70/00 , H01L23/522 , H01L49/02
CPC classification number: H01L28/57 , H01L21/324 , H01L21/76832 , H01L28/65 , H01L28/75 , H10B53/30 , H10N70/8836
Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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公开(公告)号：US11862517B1
公开(公告)日：2024-01-02
申请号：US17553486
申请日：2021-12-16
Applicant: Kepler Computing Inc.
Inventor： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
IPC: H01L21/00 , H01L21/768 , H01L23/538 , G11C11/22 , H10B53/20
CPC classification number: H01L21/76877 , G11C11/221 , H01L21/76802 , H01L23/5384 , H10B53/20
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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公开(公告)号：US11844203B1
公开(公告)日：2023-12-12
申请号：US17553469
申请日：2021-12-16
Applicant: Kepler Computing Inc.
Inventor： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
CPC classification number: H10B53/20 , G11C11/221 , H01L28/75
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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公开(公告)号：US20240276735A1
公开(公告)日：2024-08-15
申请号：US18448918
申请日：2023-08-12
Applicant: Kepler Computing Inc.
Inventor： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC classification number: H10B53/30 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05541 , H01L2224/05557 , H01L2224/05686 , H01L2224/08145 , H01L2224/80931 , H01L2924/04941 , H01L2924/04953
Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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5.发明公开公开(公告)号：US20240276734A1
公开(公告)日：2024-08-15
申请号：US18448917
申请日：2023-08-12
Applicant: Kepler Computing Inc.
Inventor： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC classification number: H10B53/20 , H01L28/55 , H01L28/91 , H01L28/92 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H10B51/20
Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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Patent Agency Ranking
公开(公告)号：US20240274651A1
公开(公告)日：2024-08-15
申请号：US18448852
申请日：2023-08-11
Applicant: Kepler Computing Inc.
Inventor： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC classification number: H01L28/60 , H01L24/32 , H01L28/55 , H01L2224/32145
Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US11871584B1
公开(公告)日：2024-01-09
申请号：US17553475
申请日：2021-12-16
Applicant: Kepler Computing Inc.
Inventor： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
CPC classification number: H10B53/30
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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8.发明公开公开(公告)号：US20230246062A1
公开(公告)日：2023-08-03
申请号：US17649534
申请日：2022-01-31
Applicant: Kepler Computing Inc.
Inventor： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC: H01L49/02 , H01L21/324 , H01L21/768 , H01L27/11507 , H01L45/00
CPC classification number: H01L28/57 , H01L21/324 , H01L21/76832 , H01L27/11507 , H01L28/65 , H01L28/75 , H01L45/147
Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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公开(公告)号：US20240347397A1
公开(公告)日：2024-10-17
申请号：US18757370
申请日：2024-06-27
Applicant: Kepler Computing Inc.
Inventor： Sasikanth Manipatruni , Niloy Mukherjee , Noriyuki Sato , Tanay Gosavi , Mauricio Manfrini , Somilkumar J. Rathi , James David Clarkson , Rajeev Kumar Dokania , Debo Olaosebikan , Amrita Mathuriya
Abstract: A method to deposit a multi-layer stack for device applications includes implementing a model driven target selection for deposition. One or more targets may be procured with an initial stoichiometric composition or elemental purity. The targets may be utilized to form the multi-layer stack, and measurements may be made of chemical composition and electrical properties of the multi-layer stack. The measurements may be compared to reference target values and if measurement results are not within tolerance, the composition of the targets can be changed to yield a successive multi-layer stack. The process can be iterated until measurement results are within tolerance of target results. Additional experimentation with post deposition thermal anneal can be performed to optimize multi-layer stack properties.
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公开(公告)号：US12010854B1
公开(公告)日：2024-06-11
申请号：US17553480
申请日：2021-12-16
Applicant: Kepler Computing Inc.
Inventor： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
CPC classification number: H10B53/30
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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