公开(公告)号：US20240380403A1

公开(公告)日：2024-11-14

申请号：US18780383

申请日：2024-07-22

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Yuan-Sheng Fang ,  Robert Menezes ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H03K19/23 ,  G06F7/501

Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

公开(公告)号：US12137574B2

公开(公告)日：2024-11-05

申请号：US18357974

申请日：2023-08-15

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Gaurav Thareja ,  Amrita Mathuriya

IPC: H10B53/30 ,  G11C11/22 ,  H01L49/02

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

公开(公告)号：US11949017B2

公开(公告)日：2024-04-02

申请号：US18067633

申请日：2022-12-16

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L21/00 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H01L29/786 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20240099018A1

公开(公告)日：2024-03-21

申请号：US18357974

申请日：2023-08-15

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Gaurav Thareja ,  Amrita Mathuriya

IPC: H10B53/30 ,  G11C11/22

CPC classification number: H10B53/30 ,  G11C11/221 ,  H01L28/56

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

公开(公告)号：US11888067B2

公开(公告)日：2024-01-30

申请号：US18181922

申请日：2023-03-10

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US11888066B2

公开(公告)日：2024-01-30

申请号：US18067653

申请日：2022-12-16

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20230284455A1

公开(公告)日：2023-09-07

申请号：US17823433

申请日：2022-08-30

Applicant: Kepler Computing Inc.

Inventor： Gaurav Thareja ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H10B53/00 ,  G11C11/22

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01L28/40

Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

公开(公告)号：US20230215952A1

公开(公告)日：2023-07-06

申请号：US18181525

申请日：2023-03-09

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/737 ,  H01L29/20 ,  H01L29/74

CPC classification number: H01L29/78618 ,  H01L29/6684 ,  H01L29/7375 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/7408 ,  H01L28/57 ,  H01L28/65 ,  H10B53/30 ,  H01L29/7869 ,  H01L28/56 ,  H10B12/312 ,  H10B12/36

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20230123515A1

公开(公告)日：2023-04-20

申请号：US18067633

申请日：2022-12-16

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

公开(公告)号：US20220200600A1

公开(公告)日：2022-06-23

申请号：US17129824

申请日：2020-12-21

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Yuan-Sheng Fang ,  Robert Menezes ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H03K19/23 ,  H01L27/118 ,  G06F7/501

Abstract: A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.