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1.发明申请METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE 有权基于可制造性，测试覆盖和可选择的诊断覆盖的组合设计集成电路的方法公开(公告)号：US20120066657A1
公开(公告)日：2012-03-15
申请号：US12880228
申请日：2010-09-13
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译： 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。
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2.发明授权Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage 有权基于可制造性，测试覆盖和可选地诊断覆盖的组合来设计集成电路的方法公开(公告)号：US08347260B2
公开(公告)日：2013-01-01
申请号：US12880228
申请日：2010-09-13
IPC分类号： G06F11/22
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译： 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。
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3.发明授权Optimizing voltage on a power plane using a host control unit to control a networked voltage regulation module array 有权使用主机控制单元优化电源平面上的电压，以控制网络电压调节模块阵列公开(公告)号：US08607080B2
公开(公告)日：2013-12-10
申请号：US13399799
申请日：2012-02-17
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。
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4.发明授权Optimizing voltage on a power plane using a networked voltage regulation module array 失效使用网络电压调节模块阵列优化电源平面上的电压公开(公告)号：US08341434B2
公开(公告)日：2012-12-25
申请号：US12037743
申请日：2008-02-26
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。
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5.发明申请UTILIZING NETWORKED 3D VOLTAGE REGULATION MODULES (VRM) TO OPTIMIZE POWER AND PERFORMANCE OF A DEVICE 有权利用网络化的3D电压调节模块（VRM）优化设备的功率和性能公开(公告)号：US20120159203A1
公开(公告)日：2012-06-21
申请号：US13399799
申请日：2012-02-17
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。
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6.发明申请Utilizing Networked Three Dimensional Voltage Regulation Modules (VRM) to Optimize Power and Performance of a Device 失效利用网络三维电压调节模块（VRM）来优化设备的功率和性能公开(公告)号：US20090217059A1
公开(公告)日：2009-08-27
申请号：US12037743
申请日：2008-02-26
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.
摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。
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公开(公告)号：US08470713B2
公开(公告)日：2013-06-25
申请号：US12966432
申请日：2010-12-13
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/76237 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L29/78
摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
摘要翻译： 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。
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8.发明申请SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS 有权用于校正集成电路芯片的系统参数变化的系统和方法，以最小化电路有限的损失公开(公告)号：US20110098838A1
公开(公告)日：2011-04-28
申请号：US12603679
申请日：2009-10-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.
摘要翻译： 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。
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9.发明授权公开(公告)号：US07935638B2
公开(公告)日：2011-05-03
申请号：US12566043
申请日：2009-09-24
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/28123 , H01L21/3185
摘要： Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.
摘要翻译： 用于增强不同基底区域中异质特征之间的周长与表面积之比的均匀性的方法和结构。 衬底上的至少一种形状包括有效减少第一衬底区域中的特征与第二衬底区域中的特征之间的周边表面积比的差异的附加边缘。 周边至表面积比的改善的均匀性降低了跨越第一和第二基底区域中的特征沉积的共形层的厚度变化。
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10.发明授权System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss 有权用于校正集成电路芯片上的系统参数变化的系统和方法，以最小化电路限制的产量损失公开(公告)号：US08301290B2
公开(公告)日：2012-10-30
申请号：US12603679
申请日：2009-10-22
IPC分类号： G06F19/00
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.
摘要翻译： 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。
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