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    SECONDARY POWER UTILIZATION DURING PEAK POWER TIMES
    2.
    发明申请
    SECONDARY POWER UTILIZATION DURING PEAK POWER TIMES 有权
    峰值功率时期的次级功率利用

    公开(公告)号：US20120324255A1

    公开(公告)日：2012-12-20

    申请号：US13593837

    申请日：2012-08-24

    申请人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    发明人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/263

    摘要： Systems and methods for selectively utilizing secondary power sources during peak power times are provided for. The method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.

    摘要翻译： 提供了用于在峰值功率时间期间选择性地利用次级电源的系统和方法。 该方法包括接收峰值功率时间的通知，以及停止使用主电源并基于该通知开始使用次级电源。

    Secondary power utilization during peak power times
    3.
    发明授权
    Secondary power utilization during peak power times 有权
    峰值功率时间的次要功率利用率

    公开(公告)号：US08301921B2

    公开(公告)日：2012-10-30

    申请号：US12056308

    申请日：2008-03-27

    申请人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    发明人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/263

    摘要： The invention generally relates to the utilization of electric power, and more particularly to systems and methods for selectively utilizing secondary power sources during peak power times. A method includes receiving a notification of a peak power time, and discontinuing use of a primary power supply and beginning use of a secondary power supply based upon the notification.

    摘要翻译： 本发明一般涉及电力的利用，更具体地涉及用于在峰值功率时间期间选择性地利用次级电源的系统和方法。 一种方法包括接收峰值功率时间的通知，以及基于该通知中断主电源的使用并开始使用次级电源。

    SWITCH TO PERFORM NON-DESTRUCTIVE AND SECURE DISABLEMENT OF IC FUNCTIONALITY UTILIZING MEMS AND METHOD THEREOF
    4.
    发明申请
    SWITCH TO PERFORM NON-DESTRUCTIVE AND SECURE DISABLEMENT OF IC FUNCTIONALITY UTILIZING MEMS AND METHOD THEREOF 有权
    切换实现使用MEMS的IC功能的非破坏性和安全性的失效及其方法

    公开(公告)号：US20120146684A1

    公开(公告)日：2012-06-14

    申请号：US12964764

    申请日：2010-12-10

    申请人： Jonathan Ebbers ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    发明人： Jonathan Ebbers ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    IPC分类号： H03K19/00

    CPC分类号： G06F21/87

    摘要： Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device is in the error state.

    摘要翻译： 提供了用于执行集成电路（IC）功能的非破坏性和安全性的禁用的结构和方法。 用于实现IC的非破坏性和安全的禁用和重新启用的结构包括初始设置为芯片使能状态的微电机械结构（MEMS）。 该结构还包括激活电路，其可操作以基于检测到的IC的预定条件将MEMS器件设置为错误状态。 当MEMS器件处于错误状态时，IC被禁止。

    Dynamic critical path detector for digital logic circuit paths
    5.
    发明授权
    Dynamic critical path detector for digital logic circuit paths 有权
    用于数字逻辑电路路径的动态关键路径检测器

    公开(公告)号：US08132136B2

    公开(公告)日：2012-03-06

    申请号：US11937111

    申请日：2007-11-08

    申请人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.

    摘要翻译： 用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。 该方法包括将第一和第二闩锁放置在关键路径附近。 第一锁存器具有包括关键路径上的数据值的输入。 该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状况，以及执行预定的校正 衡量关键路径。 本发明还涉及电路所在的设计结构。

    Processor pipeline architecture logic state retention systems and methods
    6.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07937560B2

    公开(公告)日：2011-05-03

    申请号：US12121292

    申请日：2008-05-15

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

    摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

    Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly
    7.
    发明授权
    Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly 有权
    一种用于预测间歇电力环境中的电力事件并且相应地调度集成电路的计算操作的系统和方法的结构

    公开(公告)号：US07895459B2

    公开(公告)日：2011-02-22

    申请号：US11938899

    申请日：2007-11-13

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

    摘要翻译： 一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，根据历史日志预测后续功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

    Mechanism for detection and compensation of NBTI induced threshold degradation
    8.
    发明授权
    Mechanism for detection and compensation of NBTI induced threshold degradation 有权
    NBTI诱发阈值降解的检测和补偿机制

    公开(公告)号：US07849426B2

    公开(公告)日：2010-12-07

    申请号：US11931144

    申请日：2007-10-31

    申请人： Kenneth J. Goodnow ,  Douglas W. Kemerer ,  Stephen G. Shuma ,  Oscar C. Strohacker ,  Mark S. Styduhar ,  Peter A. Twombly ,  Paul S. Zuchowski

    发明人： Kenneth J. Goodnow ,  Douglas W. Kemerer ,  Stephen G. Shuma ,  Oscar C. Strohacker ,  Mark S. Styduhar ,  Peter A. Twombly ,  Paul S. Zuchowski

    IPC分类号： G06F17/50 ,  G01R31/26

    CPC分类号： G06F17/5063

    摘要： The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.

    摘要翻译： 本发明的实施例提供了用于检测和补偿负偏压温度不稳定性（NBTI）诱导的阈值劣化的设计结构。 提供一种半导体器件，其包括至少一个应力器件，其具有施加到其栅极节点的电压和至少一个具有零栅极至源极电压的参考器件。 还提供控制器来配置设备和/或参考设备的节点电压以反映在数字和模拟电路应用中发现的设备操作的不同区域。 此外，控制器测量应力装置和参考装置之间的电流差，以确定在应力装置中是否发生了NBTI诱导的阈值劣化。 控制器还调整应力装置的输出电源电压，直到应力装置的性能与参考装置的性能匹配以解决NBTI诱发的阈值劣化。

    Redundant critical path circuits to meet performance requirement
    10.
    发明授权
    Redundant critical path circuits to meet performance requirement 失效
    冗余的关键路径电路，以满足性能要求

    公开(公告)号：US07716615B2

    公开(公告)日：2010-05-11

    申请号：US11848278

    申请日：2007-08-31

    申请人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    发明人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational.

    摘要翻译： 公开了使用冗余关键路径电路满足性能要求的方法，系统，IC和设计结构。 在一个实施例中，IC包括多个冗余关键路径电路，其中满足性能要求的多个冗余关键路径电路中的至少一个是可操作的，而其他冗余关键路径电路是不可操作的。