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公开(公告)号：US06384630B2
公开(公告)日：2002-05-07
申请号：US09760231
申请日：2001-01-12
申请人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
发明人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
IPC分类号： H03K19177
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17744 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。
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公开(公告)号：US06815981B2
公开(公告)日：2004-11-09
申请号：US10361477
申请日：2003-02-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译： 可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。
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公开(公告)号：US06392438B1
公开(公告)日：2002-05-21
申请号：US09684148
申请日：2000-10-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K1977
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译： 可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。
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公开(公告)号：US06191608B1
公开(公告)日：2001-02-20
申请号：US08851250
申请日：1997-05-05
申请人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
发明人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
IPC分类号： H03K19177
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。
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公开(公告)号：US5680061A
公开(公告)日：1997-10-21
申请号：US747194
申请日：1996-11-12
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。
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公开(公告)号：US06636936B2
公开(公告)日：2003-10-21
申请号：US09544379
申请日：2000-04-06
IPC分类号： G06F1300
CPC分类号： G06F11/1417 , G06F15/177
摘要： Apparatus and methods for configuring a plurality of programmable logic devices which include the steps of providing a source of configuration data and transferring the configuration data directly from the source to each of the programmable logic devices. In some embodiments, the methods permit the programmable logic devices to configure themselves without the intervention of an intelligent host such as a CPU, a microcontroller, or other types of intelligent logic. In other embodiments, configuration data files are used in conjunction with an intelligent host to configure the programmable logic devices. Configuration is performed at power-up or, alternatively, under user or software control.
摘要翻译： 用于配置多个可编程逻辑器件的装置和方法包括以下步骤：提供配置数据源，并将配置数据直接从源传送到每个可编程逻辑器件。 在一些实施例中，该方法允许可编程逻辑器件配置自身而不需要诸如CPU，微控制器或其他类型的智能逻辑的智能主机的介入。 在其他实施例中，配置数据文件与智能主机结合使用以配置可编程逻辑设备。 配置在上电时或在用户或软件控制下执行。
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公开(公告)号：US6052755A
公开(公告)日：2000-04-18
申请号：US709491
申请日：1996-09-06
IPC分类号： G06F11/14 , G06F15/177 , G06F13/00
CPC分类号： G06F11/1417 , G06F15/177
摘要： Apparatus and methods for configuring a plurality of programmable logic devices which include the steps of providing a source of configuration data and transferring the configuration data directly from the source to each of the programmable logic devices. In some embodiments, the methods permit the programmable logic devices to configure themselves without the intervention of an intelligent host such as a CPU, a microcontroller, or other types of intelligent logic. In other embodiments, configuration data files are used in conjunction with an intelligent host to configure the programmable logic devices. Configuration is performed at power-up or, alternatively, under user or software control.
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