公开(公告)号：US06191608B1

公开(公告)日：2001-02-20

申请号：US08851250

申请日：1997-05-05

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

IPC分类号： H03K19177

CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

公开(公告)号：US06384630B2

公开(公告)日：2002-05-07

申请号：US09760231

申请日：2001-01-12

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

IPC分类号： H03K19177

CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17748

摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

公开(公告)号：US5543730A

公开(公告)日：1996-08-06

申请号：US442801

申请日：1995-05-17

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard S. Terrill ,  Rina Raman ,  Robert R. N. Bielby

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard S. Terrill ,  Rina Raman ,  Robert R. N. Bielby

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

公开(公告)号：US06815981B2

公开(公告)日：2004-11-09

申请号：US10361477

申请日：2003-02-06

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

IPC分类号： H03K19177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

摘要翻译： 可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US06392438B1

公开(公告)日：2002-05-21

申请号：US09684148

申请日：2000-10-06

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

IPC分类号： H03K1977

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

摘要翻译： 可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US5850152A

公开(公告)日：1998-12-15

申请号：US834998

申请日：1997-04-07

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

公开(公告)号：US5850151A

公开(公告)日：1998-12-15

申请号：US834996

申请日：1997-04-07

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David E. Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David W. Mendel ,  Craig S. Lytle ,  Robert R. N. Bielby ,  Kerry Veenstra

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

摘要翻译： 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US5963049A

公开(公告)日：1999-10-05

申请号：US807561

申请日：1997-02-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

公开(公告)号：US06366121B2

公开(公告)日：2002-04-02

申请号：US09865227

申请日：2001-05-25

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： G06F738

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate “lonely register” function in modules of the regions.

摘要翻译： 可编程逻辑阵列集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域以交叉行和列的区域的二维阵列布置在器件上。 几个区域的输出信号共享一组驱动器，用于将区域输出信号应用于在区域之间传送信号的互连导体。 这节省了驱动程序资源，并增加了信号路由的灵活性。 可以使用各种方法来配置互连导体，以便节省互连导体资源。 逻辑区域可以用于直接驱动特定的输入/输出单元，由此简化到I / O单元的信号路由，并且还可能简化I / O单元的结构（例如，通过允许执行某些I / O单元功能 在相关的逻辑区域）。 区域输出信号路由灵活性也可以被增强以促进组合逻辑的同时执行和区域模块中的单独的“孤独寄存器”功能。

公开(公告)号：US5909126A

公开(公告)日：1999-06-01

申请号：US672676

申请日：1996-06-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/04 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  H03K19/04

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。