摘要:
A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.
摘要:
In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
摘要:
In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
摘要:
A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要:
A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要:
A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.
摘要:
A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.
摘要:
A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.
摘要:
A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要:
A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.