利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

59 records (took 0.016 seconds)

    RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME
    4.
    发明申请
    RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME 有权
    辐射硬化SOI结构及其制备方法

    公开(公告)号：US20130341770A1

    公开(公告)日：2013-12-26

    申请号：US13555271

    申请日：2012-07-23

    Applicant: Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC: H01L29/02

    CPC classification number: H01L21/31155 ,  H01L21/304 ,  H01L21/7624

    Abstract: An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

    Abstract translation: 首先提供包括位于基底基板和顶部半导体有源层之间的掩埋绝缘体层的SOI衬底。 然后可以在顶部半导体有源层的一部分上和/或内部形成半导体器件。 掩埋绝缘体层的与埋入绝缘体层的与顶部半导体活性层形成界面的最上表面相对的最底表面可以暴露。 然后，离子可以通过掩埋绝缘体层的最底部的表面注入埋入的绝缘体层的一部分中。 将离子注入到不会干扰埋入的绝缘体层/顶部半导体有源层界面的能量范围内，同时在掩埋的绝缘体层/顶部半导体活性层界面附近保留相当薄的部分隐埋绝缘体层。

    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets
    6.
    发明申请
    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets 审中-公开
    具有无门侧壁的翅片结构，用于多栅极Mosfets

    公开(公告)号：US20130196488A1

    公开(公告)日：2013-08-01

    申请号：US13605085

    申请日：2012-09-06

    Applicant: Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    Inventor： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC: H01L21/20

    CPC classification number: H01L29/785 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/66795

    Abstract: Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔEc) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si δ-doping layer to supply electron carriers to the III-V channel.

    Abstract translation: 提供了改进的鳍场效应晶体管（FinFET），以及用于形成FinFET鳍片的改进技术。 通过在绝缘体上形成半绝缘层，形成范围从0.05-0.6eV的足够大的导带偏移（DeltaEc）形成FinFET鳍; 在所述半绝缘层上构图外延掩模，其中所述外延掩模具有鳍的期望图案的反向图像; 在外延掩模内进行选择性外延生长; 并移除外延掩模，使得翅片保留在半绝缘层上。 半绝缘层包括例如III-V族半导体材料，并且任选地还包括用于向III-V沟道提供电子载流子的Si-δ掺杂层。

    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets
    7.
    发明申请
    Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets 审中-公开
    具有无门侧壁的翅片结构，用于多栅极Mosfets

    公开(公告)号：US20130193482A1

    公开(公告)日：2013-08-01

    申请号：US13359849

    申请日：2012-01-27

    Applicant: Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    Inventor： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC: H01L29/78 ,  H01L21/20

    CPC classification number: H01L29/785 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/66795

    Abstract: Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔEe) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si δ-doping layer to supply electron carriers to the III-V channel.

    Abstract translation: 提供了改进的鳍场效应晶体管（FinFET），以及用于形成FinFET鳍片的改进技术。 通过在绝缘体上形成半导体带偏移（DeltaEe）为0.05-0.6eV的半绝缘层，形成FinFET的鳍; 在所述半绝缘层上构图外延掩模，其中所述外延掩模具有鳍的期望图案的反向图像; 在外延掩模内进行选择性外延生长; 并移除外延掩模，使得翅片保留在半绝缘层上。 半绝缘层包括例如III-V族半导体材料，并且任选地还包括用于向III-V沟道提供电子载流子的Si-δ掺杂层。

    Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer
    8.
    发明申请
    Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer 有权
    在III-V通道材料和绝缘层之间使用带隙材料的半导体衬底

    公开(公告)号：US20130193441A1

    公开(公告)日：2013-08-01

    申请号：US13361004

    申请日：2012-01-30

    Applicant: Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    Inventor： Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

    IPC: H01L29/20 ,  H01L21/20

    CPC classification number: H01L27/12 ,  H01L29/1025 ,  H01L29/7781

    Abstract: Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔEc) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In1-xGaxAs or In1-xGaxSb, with x varying from 0 to 1. The wide bandgap material can be comprised of, for example, In1-yAlyAs, In1-yAlyP, Al1-yGayAs or In1-yGayP, with y varying from 0 to 1.

    Abstract translation: 提供了改进的半导体衬底，其在通道和绝缘体之间采用宽带隙材料。 半导体衬底包括由III-V材料构成的沟道层; 绝缘体层; 以及在沟道层和绝缘体层之间的宽带隙材料，其中沟道层和宽带隙材料之间的导带偏移（DeltaEc）在0.05eV和0.8eV之间。 沟道层可以由例如In1-xGaxAs或In1-xGaxSb组成，x的变化范围为0到1.宽带隙材料可以由例如In1-yAlyAs，In1-yAlyP，Al1-yGayAs 或In1-yGayP，y从0变化到1。

Patent Agency Ranking