公开(公告)号：US06365465B1

公开(公告)日：2002-04-02

申请号：US09272297

申请日：1999-03-19

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Yuan Taur ,  Hon-Sum P. Wong

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Yuan Taur ,  Hon-Sum P. Wong

IPC分类号： H01L21336

CPC分类号： H01L29/78654 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78687 ,  H01L29/78696

摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

摘要翻译： 制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口， 在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个 从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体 在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

公开(公告)号：US06759710B2

公开(公告)日：2004-07-06

申请号：US10051562

申请日：2002-01-18

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Yuan Taur ,  Hon-Sum P. Wong

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Yuan Taur ,  Hon-Sum P. Wong

IPC分类号： H01L2976

CPC分类号： H01L29/78654 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78687 ,  H01L29/78696

摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

摘要翻译： 制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口， 在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个 从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体 在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

公开(公告)号：US06982460B1

公开(公告)日：2006-01-03

申请号：US09612260

申请日：2000-07-07

申请人： Guy M. Cohen ,  Hon-Sum P. Wong

发明人： Guy M. Cohen ,  Hon-Sum P. Wong

IPC分类号： H01L29/76 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.

摘要翻译： 一种制造双栅极集成电路的结构和方法，包括在沟道层的每一侧上形成具有沟道层和第一绝缘层的层叠结构，在层叠结构中形成开口，在开口中形成漏极和源极区域， 去除所述层叠结构的部分以使所述沟道层的第一部分暴露，在所述沟道层上形成第一栅极电介质层，在所述第一栅极介电层上形成第一栅电极，去除所述层叠结构的部分以留下第二栅极电介质层 在所述沟道层上形成第二栅极电介质层，在所述第二栅极电介质层上形成第二栅极电极，使用自对准离子注入来掺杂所述漏极和源极区域，其中所述第一栅电极和 第二栅电极彼此独立地形成。

公开(公告)号：US06967377B2

公开(公告)日：2005-11-22

申请号：US10629014

申请日：2003-07-29

申请人： Guy M. Cohen ,  Hon-Sum P. Wong

发明人： Guy M. Cohen ,  Hon-Sum P. Wong

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78648

摘要： It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).

摘要翻译： 因此，本发明的目的是提供一种用于集成电路的结构和方法，该集成电路包括第一栅极，第二栅极以及与第一和第二栅极相邻的源极和漏极区域，其中该结构具有平面上部结构 并且第一栅极，源极和漏极区域在单个自对准过程（硅化物）中被硅化。

公开(公告)号：US07101762B2

公开(公告)日：2006-09-05

申请号：US11050366

申请日：2005-02-03

申请人： Guy M. Cohen ,  Hon-Sum P. Wong

发明人： Guy M. Cohen ,  Hon-Sum P. Wong

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.

摘要翻译： 一种制造双栅极集成电路的结构和方法，包括在沟道层的每一侧上形成具有沟道层和第一绝缘层的层叠结构，在层叠结构中形成开口，在开口中形成漏极和源极区域， 去除所述层叠结构的部分以使所述沟道层的第一部分暴露，在所述沟道层上形成第一栅极电介质层，在所述第一栅极介电层上形成第一栅电极，去除所述层叠结构的部分以留下第二栅极电介质层 在所述沟道层上形成第二栅极电介质层，在所述第二栅极电介质层上形成第二栅极电极，使用自对准离子注入来掺杂所述漏极和源极区域，其中所述第一栅电极和 第二栅电极彼此独立地形成。

公开(公告)号：US06642115B1

公开(公告)日：2003-11-04

申请号：US09690875

申请日：2000-10-18

申请人： Guy M. Cohen ,  Hon-Sum P. Wong

发明人： Guy M. Cohen ,  Hon-Sum P. Wong

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78648

摘要： It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).

摘要翻译： 因此，本发明的目的是提供一种用于集成电路的结构和方法，该集成电路包括与第一和第二栅极相邻的第一栅极，第二栅极和源极和漏极区域，其中该结构具有平面上部结构 并且第一栅极，源极和漏极区域在单个自对准过程（硅化物）中被硅化。

公开(公告)号：US06448131B1

公开(公告)日：2002-09-10

申请号：US09929182

申请日：2001-08-14

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy M. Cohen ,  Ramachandra Divakaruni ,  Christian Lavoie ,  Fenton R. McFeely

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  Y10S438/964

摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

摘要翻译： 提供了一种用于增加沟槽电容器表面积的方法。 利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。 可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。 一旦金属沉积在沟槽中，该方法是自限制的。 通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

公开(公告)号：US06946696B2

公开(公告)日：2005-09-20

申请号：US10328285

申请日：2002-12-23

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01C27/148

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US07259049B2

公开(公告)日：2007-08-21

申请号：US11146624

申请日：2005-06-07

申请人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul M Solomon ,  Min Yang

发明人： Kevin K. Chan ,  Guy M. Cohen ,  Meikei Ieong ,  Ronnen A. Roy ,  Paul M Solomon ,  Min Yang

IPC分类号： H01L21/84

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US06444578B1

公开(公告)日：2002-09-03

申请号：US09791024

申请日：2001-02-21

申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  Kevin K. Chan ,  Guy M. Cohen ,  Kathryn Wilder Guarini ,  James M. Harper ,  Christian Lavoie ,  Paul M. Solomon

发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  Kevin K. Chan ,  Guy M. Cohen ,  Kathryn Wilder Guarini ,  James M. Harper ,  Christian Lavoie ,  Paul M. Solomon

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

摘要翻译： 本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。 本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。