利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

85 条记录 (耗时 0.021 秒)

    Asymmetric epitaxy and application thereof
    1.
    发明授权
    Asymmetric epitaxy and application thereof 有权
    不对称外延及其应用

    公开(公告)号：US08198673B2

    公开(公告)日：2012-06-12

    申请号：US13080702

    申请日：2011-04-06

    申请人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

    发明人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

    IPC分类号： H01L21/00

    CPC分类号： H01L21/26586 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

    摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

    摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成栅极结构，该栅极结构包括一个栅极叠层和邻近该栅极叠层的侧壁的间隔物，并具有与第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。

    Fabrication of Field Effect Devices Using Spacers
    2.
    发明申请
    Fabrication of Field Effect Devices Using Spacers 失效
    使用Spacers制造场效应器件

    公开(公告)号：US20110171788A1

    公开(公告)日：2011-07-14

    申请号：US12684997

    申请日：2010-01-11

    申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

    发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

    摘要： A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

    摘要翻译： 一种形成场效应器件的方法包括在绝缘体上硅层（SOI）上形成栅极部分，在邻近栅极部分的SOI层上形成第一间隔元件，在SOI层上沉积间隔物材料层， 第一隔离构件和栅极部分，去除间隔物材料层的部分，以在与第一间隔件相邻的SOI层上形成第二间隔件，通过将离子注入到SOI层上形成源极区域和漏极区域 SOI层，并蚀刻以除去第二间隔件。

    Structure and method of fabricating FinFET
    5.
    发明授权
    Structure and method of fabricating FinFET 有权
    FinFET的结构和方法

    公开(公告)号：US07955928B2

    公开(公告)日：2011-06-07

    申请号：US12413836

    申请日：2009-03-30

    申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/823821 ,  H01L29/66803

    摘要： A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.

    摘要翻译： 提供了一种使用三维掺杂工艺的CMOS FinFET器件及其制造方法。 形成CMOS FinFET的方法包括在结构的第一侧和第二侧上形成翅片，并且在结构的第一侧的翅片上形成具有第一掺杂剂类型的掺杂剂材料的间隔物。 该方法还包括退火掺杂剂材料，使得第一掺杂剂类型扩散到结构的第一侧上的翅片。 该方法还包括在退火期间保护第一掺杂剂类型不扩散到结构的第二侧上的翅片。

    ASYMMETRIC EPITAXY AND APPLICATION THEREOF
    6.
    发明申请
    ASYMMETRIC EPITAXY AND APPLICATION THEREOF 有权
    不对称外延及其应用

    公开(公告)号：US20110108918A1

    公开(公告)日：2011-05-12

    申请号：US12614699

    申请日：2009-11-09

    申请人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

    发明人： Haizhou Yin ,  Xinhui Wang ,  Kevin K. Chan ,  Zhibin Ren

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

    摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

    摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成栅极结构，该栅极结构包括一个栅极叠层和邻近该栅极叠层的侧壁的间隔物，并具有与第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。

    Fabrication of field effect devices using spacers
    8.
    发明授权
    Fabrication of field effect devices using spacers 失效
    使用间隔物制造场效应器件

    公开(公告)号：US08765532B2

    公开(公告)日：2014-07-01

    申请号：US12684997

    申请日：2010-01-11

    申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

    发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

    摘要： A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

    摘要翻译： 一种形成场效应器件的方法包括在绝缘体上硅层（SOI）上形成栅极部分，在邻近栅极部分的SOI层上形成第一间隔元件，在SOI层上沉积间隔物材料层， 第一隔离构件和栅极部分，去除间隔物材料层的部分，以在与第一间隔件相邻的SOI层上形成第二间隔件，通过将离子注入到SOI层上形成源极区域和漏极区域 SOI层，并蚀刻以除去第二间隔件。

    Thin-BOX metal backgate extremely thin SOI device
    9.
    发明授权
    Thin-BOX metal backgate extremely thin SOI device 失效
    薄BOX金属背板极薄的SOI器件

    公开(公告)号：US08431994B2

    公开(公告)日：2013-04-30

    申请号：US12724555

    申请日：2010-03-16

    申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7827 ,  H01L21/7624 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

    摘要： Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.

    摘要翻译： 使用具有小于20nm厚的硅层的绝缘体上硅（SOI）结构来形成极薄的绝缘体上硅（ETSOI）半导体器件。 ETSOI器件使用由薄氮化物层封装的薄钨背栅来制造，以防止金属氧化，钨背栅的特征在于其低电阻率。 该结构还包括至少一个FET，其具有由高K金属栅极和叠加在其上的钨区域形成的栅极堆叠，栅极堆叠的占用面积利用薄SOI层作为沟道。 这样形成的SOI结构控制了薄SOI厚度和其中的掺杂剂的Vt变化。 ETSOI高K金属后盖完全耗尽器件与薄BOX结合，提供了出色的短通道控制，显着降低了漏极引起的偏置和次阈值摆幅。 本结构支持在热处理期间具有钨膜的晶片的稳定性的证据，特别是在STI和接触形成期间。

    Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions
    10.
    发明授权
    Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions 有权
    用于制造FinFET器件的方法，其包括用于限定栅极周界的掩模和用于限定鳍片区域的另一个掩模

    公开(公告)号：US08202780B2

    公开(公告)日：2012-06-19

    申请号：US12533389

    申请日：2009-07-31

    申请人： Zhibin Ren ,  Xinhui Wang ,  Kevin K. Chan ,  Ying Zhang

    发明人： Zhibin Ren ,  Xinhui Wang ,  Kevin K. Chan ,  Ying Zhang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.

    摘要翻译： 一种制造FinFET器件的方法包括：提供其上设置有掩模的衬底; 覆盖掩模的部分以限定栅极区域的周边; 去除所述掩模的未覆盖部分以暴露所述基底; 用另一掩模覆盖暴露的基底的一部分以限定至少一个鳍片区域; 通过所述掩模和所述基板形成所述至少一个翅片和所述栅极区域，所述栅极区域具有侧壁; 将所述至少一个翅片周围的绝缘层设置在所述侧壁上; 将导电材料设置在栅极区域和绝缘层上以形成栅电极，然后形成源极和漏极区域。