公开(公告)号：US07882338B2

公开(公告)日：2011-02-01

申请号：US12034066

申请日：2008-02-20

申请人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito, III ,  Robert J. Sonnelitter, III ,  Charles F. Webb

发明人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito, III ,  Robert J. Sonnelitter, III ,  Charles F. Webb

IPC分类号： G06F9/32

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844

摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.

摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

公开(公告)号：US20090210661A1

公开(公告)日：2009-08-20

申请号：US12034066

申请日：2008-02-20

申请人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  Charles F. Webb

发明人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  Charles F. Webb

IPC分类号： G06F9/312

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844

摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.

摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

公开(公告)号：US07822954B2

公开(公告)日：2010-10-26

申请号：US12034112

申请日：2008-02-20

申请人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

发明人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/383 ,  G06F9/3802 ,  G06F9/3861

摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

摘要翻译： 分支预测算法用于生成是否采用分支的预测。 取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。 执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。 当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

公开(公告)号：US20090210684A1

公开(公告)日：2009-08-20

申请号：US12034112

申请日：2008-02-20

申请人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

发明人： John W. Ward, III ,  Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

IPC分类号： G06F9/30

CPC分类号： G06F9/383 ,  G06F9/3802 ,  G06F9/3861

摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.

摘要翻译： 分支预测算法用于生成是否采用分支的预测。 取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。 执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。 当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

公开(公告)号：US08443176B2

公开(公告)日：2013-05-14

申请号：US12037042

申请日：2008-02-25

申请人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

发明人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

IPC分类号： G06F9/00

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F12/0862 ,  G06F2212/1021

摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.

摘要翻译： 一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过 基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出 如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。 相应的系统和计算机程序产品。

公开(公告)号：US20090217003A1

公开(公告)日：2009-08-27

申请号：US12037042

申请日：2008-02-25

申请人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

发明人： Robert J. Sonnelitter, III ,  James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30058 ,  G06F12/0862 ,  G06F2212/1021

摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.

摘要翻译： 一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过 基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出 如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。 相应的系统和计算机程序产品。

公开(公告)号：US20090240977A1

公开(公告)日：2009-09-24

申请号：US12051367

申请日：2008-03-19

申请人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

发明人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

IPC分类号： G06F11/14

CPC分类号： G06F11/0751 ,  G06F9/30105 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0721

摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.

摘要翻译： 提供了一种错误检测系统。 该系统包括包括一个或多个数据条目的数据阵列。 复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。 索引生成器选择性地增加引用数据数组的索引。 第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。 误差发生器根据第一个比较器的结果产生一个误差信号。

公开(公告)号：US08176406B2

公开(公告)日：2012-05-08

申请号：US12051367

申请日：2008-03-19

申请人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

发明人： Brian R. Prasky ,  Khary J. Alexander ,  James J. Bonanno

IPC分类号： G06F7/02

CPC分类号： G06F11/0751 ,  G06F9/30105 ,  G06F9/30141 ,  G06F9/3861 ,  G06F11/0721

摘要： An error detection system is provided. The system includes a data array that includes one or more data entries. A copy datastore selectively stores a copy of a first single data entry of the data array. An index generator selectively increments an index that references the data array. A first comparator compares the copy with a second single data entry from the data array based on the index. An error generator generates an error signal based on a result from the first comparator.

摘要翻译： 提供了一种错误检测系统。 该系统包括包括一个或多个数据条目的数据阵列。 复制数据存储选择性地存储数据阵列的第一单个数据条目的副本。 索引生成器选择性地增加引用数据数组的索引。 第一个比较器根据索引将该副本与数据数组中的第二个单个数据条目进行比较。 误差发生器根据第一个比较器的结果产生一个误差信号。

公开(公告)号：US20130339683A1

公开(公告)日：2013-12-19

申请号：US13523170

申请日：2012-06-14

申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

公开(公告)号：US08874885B2

公开(公告)日：2014-10-28

申请号：US12029543

申请日：2008-02-12

申请人： James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

发明人： James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/3848

摘要： Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.

摘要翻译： 实施例涉及减轻前瞻分支预测延迟。 一个方面包括在指令高速缓存中接收用于在微处理器流水线中取指令的指令地址。 另一方面包括在耦合到微处理器流水线的分支存在预测器中接收指令地址。 另一方面包括通过分支存在预测器确定在所取出的指令中存在分支指令，其中分支指令可由分支目标缓冲器预测，并且未写入分支目标缓冲器的指令地址的任何指示也是 没有写入分支存在预测器。 另一方面包括：基于从分支存在预测器接收到分支指令的指示，保持分支指令。 另一方面包括基于从分支目标缓冲器接收到与分支指令相对应的分支预测，将所述保持的分支指令释放到流水线。