公开(公告)号：US20110204951A1

公开(公告)日：2011-08-25

申请号：US12843995

申请日：2010-07-27

申请人： Ki Han KIM ,  Hyun Woo LEE ,  Won Joo YUN

发明人： Ki Han KIM ,  Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L5/00

CPC分类号： G11C5/147

摘要： A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.

摘要翻译： 用于产生内部电压的半导体装置包括控制代码输出块和内部电压产生块。 控制代码输出块被配置为输出具有与内部电压的电压电平对应的代码值的可变代码。 内部电压生成块被配置为将可变代码与设置代码进行比较，并且根据比较来控制内部电压的电压电平。

公开(公告)号：US20100308884A1

公开(公告)日：2010-12-09

申请号：US12645630

申请日：2009-12-23

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Ki Han KIM

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Ki Han KIM

IPC分类号： G06F1/04

CPC分类号： G06F1/12

摘要： A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.

摘要翻译： 半导体集成电路中的时钟接收器包括：第一时钟缓冲器，被配置为缓冲外部时钟以响应于第一操作信号产生低频缓冲时钟; 第二时钟缓冲器，被配置为缓冲所述外部时钟以响应于第二操作信号产生高频缓冲时钟; 以及内部时钟生成单元，被配置为接收低频缓冲时钟和高频缓冲时钟，以控制第一操作信号和第二操作信号的状态并产生内部时钟。

公开(公告)号：US20100289542A1

公开(公告)日：2010-11-18

申请号：US12493804

申请日：2009-06-29

申请人： Won Joo YUN ,  Hyun Woo LEE ,  Ki Han KIM

发明人： Won Joo YUN ,  Hyun Woo LEE ,  Ki Han KIM

IPC分类号： H03L7/06 ,  H03K5/04

CPC分类号： H03L7/0814 ,  H03K5/04 ,  H03K5/1565

摘要： A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.

摘要翻译： 半导体集成电路包括：频率确定单元，被配置为确定半导体集成电路的操作速度并产生频率区域信号; 占空比控制单元，被配置为检测DLL时钟的占空比并产生占空比控制信号; 占空比校正单元，被配置为通过响应于频域信号校正输入时钟的占空比并响应于占空比控制信号来产生校正时钟; 以及被配置为通过控制校正时钟的相位来产生DLL时钟的DLL（延迟锁定环路）。

公开(公告)号：US20130135038A1

公开(公告)日：2013-05-30

申请号：US13611298

申请日：2012-09-12

申请人： Ki Han KIM ,  Hyun Woo LEE ,  Dae Han KWON ,  Chul Woo KIM ,  Soo Bin LIM

发明人： Ki Han KIM ,  Hyun Woo LEE ,  Dae Han KWON ,  Chul Woo KIM ,  Soo Bin LIM

IPC分类号： G05F1/10

CPC分类号： H03K19/094 ,  H03K19/0013 ,  H03K19/09482

摘要： A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.

摘要翻译： 一种半导体装置，包括电源改变单元。 电源改变单元被配置为接收使能信号和电源电压，根据使能信号产生第一电压或第二电压，根据电平信号改变第二电压的电压电平，并且提供第一电压或 第二电压作为内部电路的驱动电压，其中内部电路接收第一输入信号以输出第二输入信号。

公开(公告)号：US20110241733A1

公开(公告)日：2011-10-06

申请号：US12981453

申请日：2010-12-29

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03K5/01

CPC分类号： G11C7/1066 ,  G11C7/222

摘要： An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.

摘要翻译： 输出使能信号生成电路包括等待解码器，锁存单元，延迟复用器和使能设置单元。 延迟解码器被配置为解码模式寄存器集代码并生成第一和第二CAS等待时间信息。 锁存单元被配置为输出锁存的第一和第二等待时间信息作为第一和第二等待时间信号。 延迟复用器被配置为响应于芯片选择信号而输出第一或第二等待时间信号作为输出CAS等待时间信号。 使能设置单元被配置为设置输出使能信号的使能定时。

公开(公告)号：US20120044002A1

公开(公告)日：2012-02-23

申请号：US12983187

申请日：2010-12-31

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03L7/06 ,  H03K7/08

CPC分类号： H03L7/0816

摘要： A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal.

摘要翻译： 一种半导体装置，包括：更新脉冲发生单元，被配置为基于时钟的频率在每第一周期产生更新脉冲;以及控制单元，被配置为响应于输入信号和更新脉冲来控制输出信号，使得 输出信号根据输入信号而变化。

公开(公告)号：US20110242905A1

公开(公告)日：2011-10-06

申请号：US12981815

申请日：2010-12-30

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： G11C7/10

CPC分类号： H03K3/02 ,  G11C5/02

摘要： A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

摘要翻译： 模块控制电路包括：输入单元，被配置为从多个数据输入/输出引脚接收多个数据信号，并输出识别信号和内部命令信号。 闩锁单元被配置为根据第一使能信号锁定识别信号以输出第一组识别信号，根据第二使能信号锁存识别信号以输出第二组识别信号，并锁存内部命令信号 根据第二使能信号输出组指令信号。 比较器被配置为将第一组识别信号与第二组识别信号进行比较，并产生选择信号。 复用器被配置为响应于选择信号选择组命令信号和模块命令信号之一作为输入命令。

公开(公告)号：US20110241742A1

公开(公告)日：2011-10-06

申请号：US13028253

申请日：2011-02-16

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： G11C7/1072 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  H03L7/0818

摘要： A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.

摘要翻译： 数据输出控制电路包括DLL电路和延迟检测单元。 DLL电路被配置为通过延迟从外部时钟产生的第一内部时钟来产生第二内部时钟，将第一内部时钟的相位与第二内部时钟的相位进行比较，并生成DLL时钟。 所述延迟检测单元被配置为根据设定的时间间隔的比较结果和延迟所述第一内部时钟的延迟时间间隔来生成其逻辑电平变化的感测信号，以便产生所述第二内部时钟。

公开(公告)号：US20110128059A1

公开(公告)日：2011-06-02

申请号：US12648422

申请日：2009-12-29

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.

摘要翻译： 提供了一种占空比校正电路，用于补偿当时钟信号发生器发生故障或发生信号传输线路故障时引起的占空比误差。 占空比校正电路被配置为根据占空比来选择差分信号之一作为输入信号。 占空比校正电路还被配置为将输入信号和通过将输入信号延迟通过根据占空比调整的延迟时间而获得的信号组合。 占空比校正电路还被配置为产生组合信号作为占空比校正信号。

公开(公告)号：US20130154702A1

公开(公告)日：2013-06-20

申请号：US13563863

申请日：2012-08-01

申请人： Ki Han KIM ,  Ja Beom KOO

发明人： Ki Han KIM ,  Ja Beom KOO

IPC分类号： H03L7/089

CPC分类号： H03L7/089

摘要： A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

摘要翻译： 占空比校正电路包括：占空比校正单元，被配置为根据占空比校正码校正输入时钟信号的占空比，并生成输出时钟信号; 占空比检测部，被配置为检测所述输出时钟信号的占空比并产生上下信号; 噪声检测信号生成部，被配置为检测所述上下信号的变化并生成所述噪声检测信号; 以及占空比校正控制单元，被配置为响应于噪声检测信号和上下信号产生占空比校正码。