公开(公告)号：US20110204951A1

公开(公告)日：2011-08-25

申请号：US12843995

申请日：2010-07-27

申请人： Ki Han KIM ,  Hyun Woo LEE ,  Won Joo YUN

发明人： Ki Han KIM ,  Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L5/00

CPC分类号： G11C5/147

摘要： A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.

摘要翻译： 用于产生内部电压的半导体装置包括控制代码输出块和内部电压产生块。 控制代码输出块被配置为输出具有与内部电压的电压电平对应的代码值的可变代码。 内部电压生成块被配置为将可变代码与设置代码进行比较，并且根据比较来控制内部电压的电压电平。

公开(公告)号：US20100289542A1

公开(公告)日：2010-11-18

申请号：US12493804

申请日：2009-06-29

申请人： Won Joo YUN ,  Hyun Woo LEE ,  Ki Han KIM

发明人： Won Joo YUN ,  Hyun Woo LEE ,  Ki Han KIM

IPC分类号： H03L7/06 ,  H03K5/04

CPC分类号： H03L7/0814 ,  H03K5/04 ,  H03K5/1565

摘要： A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.

摘要翻译： 半导体集成电路包括：频率确定单元，被配置为确定半导体集成电路的操作速度并产生频率区域信号; 占空比控制单元，被配置为检测DLL时钟的占空比并产生占空比控制信号; 占空比校正单元，被配置为通过响应于频域信号校正输入时钟的占空比并响应于占空比控制信号来产生校正时钟; 以及被配置为通过控制校正时钟的相位来产生DLL时钟的DLL（延迟锁定环路）。

公开(公告)号：US20120194231A1

公开(公告)日：2012-08-02

申请号：US13442426

申请日：2012-04-09

申请人： Won Joo YUN ,  Hyun Woo LEE ,  Dong Suk SHIN

发明人： Won Joo YUN ,  Hyun Woo LEE ,  Dong Suk SHIN

IPC分类号： H03L7/08

CPC分类号： H03L7/0812

摘要： A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

摘要翻译： 一种控制功率控制电路的方法包括：当延迟锁定环路（DLL）电路的延迟锁定操作完成时，使能电源切断信号，在预定时间内禁用电源切断信号，并检测参考时钟 以及反馈时钟，基于检测结果来重新确定是否启用电源切断信号。

公开(公告)号：US20120007646A1

公开(公告)日：2012-01-12

申请号：US13237083

申请日：2011-09-20

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818

摘要： A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.

摘要翻译： 延迟锁定环路（DLL）电路包括延迟线，其被配置为通过响应于延迟控制信号延迟参考时钟信号来产生延迟时钟信号，该延迟线具有两个或多个初始激活点，其中初始激活点是 根据延迟控制信号的初始值选择; 延迟补偿单元，被配置为通过将所述延迟时钟信号延迟预定时间来产生反馈时钟信号; 相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号; 以及延迟控制单元，被配置为响应于相位检测信号而产生延迟控制信号。

公开(公告)号：US20080001642A1

公开(公告)日：2008-01-03

申请号：US11683528

申请日：2007-03-08

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/00

CPC分类号： H03L7/0812 ,  H03L7/0818 ,  H03L7/087

摘要： A delay-locked loop apparatus includes at least a rising-clock delay-locked circuit, a falling-clock delay-locked circuit, and a duty cycle compensation circuit. The rising-clock delay-locked circuit detects the phase difference between a first clock inputted as a reference clock and a second clock obtained by replica-delaying the first clock, and then delay-locks the first clock and outputs a rising clock. The falling-clock delay-locked circuit detects the phase difference between an inverted clock of the first clock and the rising clock after a delay locking operation with respect to the rising clock, delay-locks an inverted clock of the first clock and outputs a falling clock. The duty cycle compensation circuit compensates duty cycles of the delay-locked rising clock and falling clock, and the falling-clock delay-locked circuit includes a divider for separately dividing the inverted clock and the delay-locked rising clock.

摘要翻译： 延迟锁定环路装置至少包括上升时钟延迟锁定电路，下降时钟延迟锁定电路和占空比补偿电路。 上升时钟延迟锁定电路检测作为参考时钟输入的第一时钟与通过复制延迟第一时钟而获得的第二时钟之间的相位差，然后延迟锁定第一时钟并输出上升时钟。 下降时钟延迟锁定电路检测在相对于上升时钟的延迟锁定操作之后第一时钟的反相时钟和上升时钟之间的相位差，延迟锁定第一时钟的反相时钟并输出下降 时钟。 占空比补偿电路补偿延迟锁定上升时钟和下降时钟的占空比，下降时钟延迟锁定电路包括一个分频器，用于分开反相时钟和延迟锁定上升时钟。

公开(公告)号：US20100117695A1

公开(公告)日：2010-05-13

申请号：US12344799

申请日：2008-12-29

申请人： Hyun Woo LEE ,  Won Joo YUN

发明人： Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0995 ,  H03L2207/06

摘要： A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.

公开(公告)号：US20100109725A1

公开(公告)日：2010-05-06

申请号：US12345136

申请日：2008-12-29

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/1565

摘要： A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.

摘要翻译： 延迟锁定环（DLL）电路包括占空比校正单元，其被配置为响应于占空比校正信号来校正参考时钟信号的占空比并产生校正时钟信号。 DLL电路的反馈回路对校正时钟信号执行延迟锁定操作，并产生输出时钟信号。 第一占空比检测单元检测校正时钟信号的占空比并产生第一检测信号，第二占空比检测单元检测输出时钟信号的占空比并产生第二检测信号。 最后，占空比控制单元响应于第一检测信号和第二检测信号产生占空比校正信号，以执行占空比校正。

公开(公告)号：US20110102035A1

公开(公告)日：2011-05-05

申请号：US12648380

申请日：2009-12-29

申请人： Hyun Woo LEE ,  Won Joo YUN

发明人： Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805 ,  H03L7/095

摘要： A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal.

摘要翻译： 提供半导体集成电路。 半导体集成电路包括：响应于多个延迟控制信号而将输入时钟信号延迟预定时间的延迟锁定环（DLL）输出块，并提供DLL时钟信号; 锁定控制块，被配置为比较参考时钟信号的相位和反馈时钟信号的相位，并且响应于所述多个延迟控制信号使参考时钟信号的相位和反馈时钟信号的相位同步; 以及锁定检测块，被配置为检测参考时钟信号的相位和反馈时钟信号的相位是否同步，并且DLL时钟信号被锁定，其中，当DLL时钟信号被锁定时，锁定控制块提供 通过将输入时钟信号除以n（其中n是等于或大于2的自然数）获得的参考时钟信号作为内部DLL时钟信号。

公开(公告)号：US20110074479A1

公开(公告)日：2011-03-31

申请号：US12883730

申请日：2010-09-16

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

摘要翻译： 延迟锁定环（DLL）装置包括将参考时钟转换为上升时钟的第一延迟单元。 第二延迟单元将参考时钟转换为下降时钟，复制延迟单元复制延迟上升时钟。 第一相位检测器比较参考时钟和延迟上升时钟的相位，以输出对应于比较相位的第一检测信号。 控制器根据第一相位检测器的第一检测信号，将上升时钟的上升沿与参考时钟的上升沿同步。 第二相位检测器比较同步上升时钟和同步时钟的相位，以输出对应于比较相位的第二检测信号。 DLL装置通过采用单个复制延迟单元来补偿外部时钟和数据之间以及外部和内部时钟之间的偏差。

公开(公告)号：US20100301911A1

公开(公告)日：2010-12-02

申请号：US12855244

申请日：2010-08-12

申请人： Hyun Woo LEE ,  Won Joo YUN

发明人： Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0995 ,  H03L2207/06

摘要： A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.

摘要翻译： 提出了具有时钟信号发生电路和数据输出电路的半导体存储装置。 该装置包括延迟锁定环（DLL），锁相环（PLL），频率鉴别单元和数据输出缓冲器。 DLL电路被配置为负时延时钟信号以产生DLL时钟信号。 PLL电路被配置为接收DLL时钟信号以响应于DLL时钟信号的频率产生控制电压，并且产生与控制电压电平对应的频率的PLL时钟信号。 频率鉴别单元被配置为根据控制电压的电平来识别DLL时钟信号的频率，以产生频率鉴别信号。 数据输出缓冲器配置为接收DLL时钟信号或PLL时钟信号以缓冲输出数据信号。