公开(公告)号：US20090285009A1

公开(公告)日：2009-11-19

申请号：US12453529

申请日：2009-05-14

申请人： Ki-Sung Kim ,  Byung-Gil Choi ,  Young-Ran Kim ,  Jong-Chul Park

发明人： Ki-Sung Kim ,  Byung-Gil Choi ,  Young-Ran Kim ,  Jong-Chul Park

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C5/14

CPC分类号： G11C13/0023 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/72

摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines.

摘要翻译： 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件可以包括存储单元阵列，其包括具有取决于存储的数据的可变电阻等级的多个非易失性存储单元的阵列。 字线可以与非易失性存储单元的每一列耦合。 局部位线可以与非易失性存储器单元的每一行耦合。 全局位线可以选择性地与多个局部位线耦合。

公开(公告)号：US08184468B2

公开(公告)日：2012-05-22

申请号：US12453529

申请日：2009-05-14

申请人： Ki-Sung Kim ,  Byung-Gil Choi ,  Young-Ran Kim ,  Jong-Chul Park

发明人： Ki-Sung Kim ,  Byung-Gil Choi ,  Young-Ran Kim ,  Jong-Chul Park

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/72

摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines.

摘要翻译： 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件可以包括存储单元阵列，其包括具有取决于存储的数据的可变电阻等级的多个非易失性存储单元的阵列。 字线可以与非易失性存储单元的每一列耦合。 局部位线可以与非易失性存储器单元的每一行耦合。 全局位线可以选择性地与多个局部位线耦合。

公开(公告)号：US20130009226A1

公开(公告)日：2013-01-10

申请号：US13540816

申请日：2012-07-03

申请人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894

摘要： A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.

摘要翻译： DRAM器件包括具有岛形状的有源区和掩埋栅极图案的衬底。 掩模图案位于掩埋栅极图案的部分之间的衬底的上表面部分之上。 封盖绝缘层填充掩模图案的部分之间的间隙。 第一焊盘接触件穿透封盖绝缘层和掩模图案，并且与有源区域中的基板的第一部分接触。 第二焊盘触点位于封盖绝缘层下方，并且接触位于第一焊盘触点两侧的有源区域中的基板的第二部分。 间隔物位于第一和第二焊盘触点之间，以使第一和第二焊盘触点绝缘。 提供了构造成与第一焊盘触点电连接的位线和被配置为与第二焊盘触点电连接的电容器。

公开(公告)号：US08067285B2

公开(公告)日：2011-11-29

申请号：US12968711

申请日：2010-12-15

申请人： Jong-Chul Park ,  Chan-Mi Lee ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Chan-Mi Lee ,  Sang-Sup Jeong

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/4236 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66621

摘要： In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

摘要翻译： 在形成导电层结构的方法和制造凹槽沟道晶体管的方法中，第一绝缘层和第一导电层依次形成在具有第一区域的第二区域的基板上， 形成区域在第一区域。 通过蚀刻衬底的暴露区域，在凹部形成区域中形成凹部。 第二绝缘层共形地形成在凹槽的侧壁和底部上。 在第二绝缘层上形成第二导电层图案以填充凹部的一部分。 在第二导电层图案和凹部的侧壁上的第二绝缘层上形成间隔物。 在第二导电层图案和间隔物上形成第三导电层图案以填充凹部。

公开(公告)号：US20100172815A1

公开(公告)日：2010-07-08

申请号：US12601523

申请日：2007-12-04

申请人： Ho Sung Park ,  Sharad D. Bhagat ,  Jong-Hyun Lim ,  Young-Chul Joung ,  Jong-Chul Park ,  Seung-Yong Jee

发明人： Ho Sung Park ,  Sharad D. Bhagat ,  Jong-Hyun Lim ,  Young-Chul Joung ,  Jong-Chul Park ,  Seung-Yong Jee

IPC分类号： C01B33/141

CPC分类号： C01B33/1585 ,  C01B33/143

摘要： Disclosed is a method of manufacturing superhydrophobic silica-based powder, including adding a water glass solution, which is not subjected to ion exchange, serving as a precursor, with an organosilane compound having an alkaline pH and an inorganic acid to thus subject the water glass solution to surface modification and gelation, thereby producing hydrogel, immersing the hydrogel in a nonpolar solvent to thus subject the hydrogel to solvent exchange and Na+ removal, and drying the hydrogel, subjected to solvent exchange, at ambient pressure, thereby manufacturing aerogel powder. This invention is very important from an industrial point of view because it involves a very simple process and realizes economic benefits.

摘要翻译： 公开了一种制造超疏水性二氧化硅基粉末的方法，包括将不进行离子交换的水玻璃溶液与具有碱性pH和无机酸的有机硅烷化合物一起添加作为前体，从而使水玻璃 溶液进行表面改性和凝胶化，由此制备水凝胶，将水凝胶浸入非极性溶剂中，从而使水凝胶进行溶剂交换和Na +去除，并在环境压力下干燥进行溶剂交换的水凝胶，从而制备气凝胶粉末。 本发明从工业角度来看是非常重要的，因为它涉及到非常简单的过程并实现经济效益。

公开(公告)号：US07160789B2

公开(公告)日：2007-01-09

申请号：US10969348

申请日：2004-10-19

申请人： Jong-Chul Park

发明人： Jong-Chul Park

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L27/10876

摘要： A shallow trench isolation (STI) structure and a method of forming the STI structure. The STI structure defines an active region formed with a recess channel transistor. The STI structure includes a STI trench has a laterally curved rounding portion on the bottom of the recess channel trench. In order to form the STI trench with the rounding portion, a semiconductor substrate is selectively and anisotropically dry etched to form the trench. Then, the semiconductor substrate is isotropically etched around the bottom height of the recess channel trench to form the rounding portion, and then further anisotropically dry etched, thereby forming the STI trench. After an insulating layer that fill the STI trench is formed on the resultant structure, an upper surface of the resultant structure is planarized to expose a surface of the semiconductor substrate.

摘要翻译： 浅沟槽隔离（STI）结构和形成STI结构的方法。 STI结构限定形成有凹槽通道晶体管的有源区。 STI结构包括STI沟槽，其在凹槽沟槽的底部上具有侧向弯曲的圆形部分。 为了形成具有圆化部分的STI沟槽，选择性地并各向异性地干蚀刻半导体衬底以形成沟槽。 然后，围绕凹槽沟槽的底部高度各向同性地蚀刻半导体衬底，以形成圆化部分，然后进一步各向异性干蚀刻，从而形成STI沟槽。 在所得结构上形成填充STI沟槽的绝缘层之后，将所得结构的上表面平坦化以暴露半导体衬底的表面。

公开(公告)号：US20050087832A1

公开(公告)日：2005-04-28

申请号：US10969348

申请日：2004-10-19

申请人： Jong-Chul Park

发明人： Jong-Chul Park

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/8238 ,  H01L21/76 ,  H01L29/00

CPC分类号： H01L21/76232 ,  H01L27/10876

摘要： A shallow trench isolation (STI) structure and a method of forming the STI structure. The STI structure defines an active region formed with a recess channel transistor. The STI structure includes a STI trench has a laterally curved rounding portion on the bottom of the recess channel trench. In order to form the STI trench with the rounding portion, a semiconductor substrate is selectively and anisotropically dry etched to form the trench. Then, the semiconductor substrate is isotropically etched around the bottom height of the recess channel trench to form the rounding portion, and then further anisotropically dry etched, thereby forming the STI trench. After an insulating layer that fill the STI trench is formed on the resultant structure, an upper surface of the resultant structure is planarized to expose a surface of the semiconductor substrate.

摘要翻译： 浅沟槽隔离（STI）结构和形成STI结构的方法。 STI结构限定形成有凹槽通道晶体管的有源区。 STI结构包括STI沟槽，其在凹槽沟槽的底部上具有侧向弯曲的圆形部分。 为了形成具有圆化部分的STI沟槽，选择性地并各向异性地干蚀刻半导体衬底以形成沟槽。 然后，围绕凹槽沟槽的底部高度各向同性地蚀刻半导体衬底，以形成圆化部分，然后进一步各向异性干蚀刻，从而形成STI沟槽。 在所得结构上形成填充STI沟槽的绝缘层之后，将所得结构的上表面平坦化以暴露半导体衬底的表面。

公开(公告)号：US5510788A

公开(公告)日：1996-04-23

申请号：US194448

申请日：1994-02-09

申请人： Hochang Jeong ,  Jong-Chul Park

发明人： Hochang Jeong ,  Jong-Chul Park

IPC分类号： H03M7/14 ,  G11B20/14 ,  H03M5/14 ,  H03M7/42

CPC分类号： G11B20/1426 ,  H03M5/145

摘要： An apparatus for converting source data into modulation data includes a compressed look-up table based on a conversion correlation, a non-effective data discriminator, a group discriminator, an output flag generator, a flag modulator, a control signal generator and an output compensator. A first address having the source data and a original input flag and a second address having the source data and a modulated input flag are sequentially applied to the look-up table which in turn generates first tentative data and a first tentative flag with respect to the first address, generates second tentative data and a second tentative flag with respect to the second address, and produces unique non-effective data when non-effective data is applied. The group discriminator produces a group discrimination signal based on the source data, the non-effective data discriminator produces a non-effective data detection signal when the first tentative data is non-effective data, the output flag generator produces an output flag based on one of the tentative flags and the non-effective data detection signal, and the flag modulator sequentially produces the original input flag and the moduated input flag based on the non-effective data detection signal and output of the output flag generator. The control signal generator produces a control signal based on the non-effective data detection signal and the group discrimination signal. The output compensator produces the modulation data, by modulating the second tentative data in accordance with the control signal.

摘要翻译： 用于将源数据转换成调制数据的装置包括基于转换相关的压缩查找表，非有效数据鉴别器，组鉴别器，输出标志发生器，标志调制器，控制信号发生器和输出补偿器 。 具有源数据和原始输入标志的第一地址以及具有源数据和调制输入标志的第二地址被顺序地施加到查找表，该查找表依次产生关于第一暂定数据和第一临时标志 第一地址，相对于第二地址生成第二临时数据和第二临时标志，并且当应用非有效数据时产生唯一的非有效数据。 组识别器基于源数据产生组鉴别信号，当第一临时数据是非有效数据时，非有效数据鉴别器产生非有效数据检测信号，输出标志发生器产生基于一个信号的输出标志 的标志调制器根据无效数据检测信号和输出标志发生器的输出顺序产生原始输入标志和调制输入标志。 控制信号发生器基于非有效数据检测信号和组识别信号产生控制信号。 输出补偿器通过根据控制信号调制第二临时数据来产生调制数据。

公开(公告)号：US08906763B2

公开(公告)日：2014-12-09

申请号：US13540816

申请日：2012-07-03

申请人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/768

CPC分类号： H01L27/10888 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894

摘要： A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.

摘要翻译： DRAM器件包括具有岛形状的有源区和掩埋栅极图案的衬底。 掩模图案位于掩埋栅极图案的部分之间的衬底的上表面部分之上。 封盖绝缘层填充掩模图案的部分之间的间隙。 第一焊盘接触件穿透封盖绝缘层和掩模图案，并且与有源区域中的基板的第一部分接触。 第二焊盘触点位于封盖绝缘层下方，并且接触位于第一焊盘触点两侧的有源区域中的基板的第二部分。 间隔物位于第一和第二焊盘触点之间，以使第一和第二焊盘触点绝缘。 提供了构造成与第一焊盘触点电连接的位线和被配置为与第二焊盘触点电连接的电容器。

公开(公告)号：US08778757B2

公开(公告)日：2014-07-15

申请号：US13540996

申请日：2012-07-03

申请人： Jong-Chul Park ,  Sang-sup Jeong

发明人： Jong-Chul Park ,  Sang-sup Jeong

IPC分类号： H01L21/8242

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876

摘要： In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.

摘要翻译： 在制造DRAM器件的方法中，在衬底中形成掩埋型栅极。 掩埋型栅极上形成封盖绝缘层图案。 形成填充封盖绝缘层图案的部分之间的间隙的导电层图案，以及覆盖导电层图案和封盖绝缘层图案的绝缘夹层。 蚀刻绝缘中间层，导电层图案，封盖绝缘层图案和基板的上部以形成开口，以及与第一焊盘区域接触的第一焊盘电极。 间隔件形成在对应于第二垫区域的开口的侧壁上。 第二焊盘电极形成在开口中。 形成与第二焊盘电极电连接的位线和与第一焊盘电极电连接的电容器。