公开(公告)号：US20130009226A1

公开(公告)日：2013-01-10

申请号：US13540816

申请日：2012-07-03

申请人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894

摘要： A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.

摘要翻译： DRAM器件包括具有岛形状的有源区和掩埋栅极图案的衬底。 掩模图案位于掩埋栅极图案的部分之间的衬底的上表面部分之上。 封盖绝缘层填充掩模图案的部分之间的间隙。 第一焊盘接触件穿透封盖绝缘层和掩模图案，并且与有源区域中的基板的第一部分接触。 第二焊盘触点位于封盖绝缘层下方，并且接触位于第一焊盘触点两侧的有源区域中的基板的第二部分。 间隔物位于第一和第二焊盘触点之间，以使第一和第二焊盘触点绝缘。 提供了构造成与第一焊盘触点电连接的位线和被配置为与第二焊盘触点电连接的电容器。

公开(公告)号：US08906763B2

公开(公告)日：2014-12-09

申请号：US13540816

申请日：2012-07-03

申请人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Byung-Jin Kang ,  Sang-Sup Jeong

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/768

CPC分类号： H01L27/10888 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894

摘要： A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.

摘要翻译： DRAM器件包括具有岛形状的有源区和掩埋栅极图案的衬底。 掩模图案位于掩埋栅极图案的部分之间的衬底的上表面部分之上。 封盖绝缘层填充掩模图案的部分之间的间隙。 第一焊盘接触件穿透封盖绝缘层和掩模图案，并且与有源区域中的基板的第一部分接触。 第二焊盘触点位于封盖绝缘层下方，并且接触位于第一焊盘触点两侧的有源区域中的基板的第二部分。 间隔物位于第一和第二焊盘触点之间，以使第一和第二焊盘触点绝缘。 提供了构造成与第一焊盘触点电连接的位线和被配置为与第二焊盘触点电连接的电容器。

公开(公告)号：US08067285B2

公开(公告)日：2011-11-29

申请号：US12968711

申请日：2010-12-15

申请人： Jong-Chul Park ,  Chan-Mi Lee ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Chan-Mi Lee ,  Sang-Sup Jeong

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/4236 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66621

摘要： In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

摘要翻译： 在形成导电层结构的方法和制造凹槽沟道晶体管的方法中，第一绝缘层和第一导电层依次形成在具有第一区域的第二区域的基板上， 形成区域在第一区域。 通过蚀刻衬底的暴露区域，在凹部形成区域中形成凹部。 第二绝缘层共形地形成在凹槽的侧壁和底部上。 在第二绝缘层上形成第二导电层图案以填充凹部的一部分。 在第二导电层图案和凹部的侧壁上的第二绝缘层上形成间隔物。 在第二导电层图案和间隔物上形成第三导电层图案以填充凹部。

公开(公告)号：US08778757B2

公开(公告)日：2014-07-15

申请号：US13540996

申请日：2012-07-03

申请人： Jong-Chul Park ,  Sang-sup Jeong

发明人： Jong-Chul Park ,  Sang-sup Jeong

IPC分类号： H01L21/8242

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876

摘要： In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.

摘要翻译： 在制造DRAM器件的方法中，在衬底中形成掩埋型栅极。 掩埋型栅极上形成封盖绝缘层图案。 形成填充封盖绝缘层图案的部分之间的间隙的导电层图案，以及覆盖导电层图案和封盖绝缘层图案的绝缘夹层。 蚀刻绝缘中间层，导电层图案，封盖绝缘层图案和基板的上部以形成开口，以及与第一焊盘区域接触的第一焊盘电极。 间隔件形成在对应于第二垫区域的开口的侧壁上。 第二焊盘电极形成在开口中。 形成与第二焊盘电极电连接的位线和与第一焊盘电极电连接的电容器。

公开(公告)号：US20060113590A1

公开(公告)日：2006-06-01

申请号：US11285558

申请日：2005-11-22

申请人： Ji-Hae Kim ,  Ji-Young Kim ,  Jong-Chul Park ,  Yong-Sun Ko ,  Sang-Sup Jeong

发明人： Ji-Hae Kim ,  Ji-Young Kim ,  Jong-Chul Park ,  Yong-Sun Ko ,  Sang-Sup Jeong

IPC分类号： H01L29/94

CPC分类号： H01L29/66621 ,  H01L29/7834

摘要： An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first etching process. A protection layer pattern is formed on a sidewall of the first recess. A second recess is formed beneath the first recess. The second recess has a width substantially larger than that of the first recess. The second recess is formed by a second etching process using an etching gas containing an SF6 gas, a Cl2 gas and an O2 gas. A gate insulation layer is formed on surfaces of the first and the second recesses. The second recess having an enlarged shape may reduce a width of the junction between the gate electrode and the isolation layer so that a leakage current generated through the junction may decrease.

摘要翻译： 具有第一深度的隔离层由衬底的上表面形成。 在衬底中形成包括结的源/漏区。 每个结点具有比第一深度基本上小的第二深度。 通过第一蚀刻工艺在衬底中形成第一凹部。 在第一凹部的侧壁上形成保护层图案。 在第一凹部下面形成第二凹部。 第二凹部的宽度显着大于第一凹部的宽度。 第二凹槽通过使用含有SF 6气体，Cl 2气体和O 2气体的蚀刻气体的第二蚀刻工艺形成 。 在第一和第二凹部的表面上形成栅极绝缘层。 具有放大形状的第二凹部可以减小栅电极和隔离层之间的结的宽度，使得通过结可以产生的漏电流可能减小。

公开(公告)号：US20050196921A1

公开(公告)日：2005-09-08

申请号：US11033447

申请日：2005-01-12

申请人： Yong-Woo Lee ,  Jong-Chul Park ,  O-Ik Kwon ,  Sang-Sup Jeong

发明人： Yong-Woo Lee ,  Jong-Chul Park ,  O-Ik Kwon ,  Sang-Sup Jeong

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

摘要翻译： 一种通过在其上形成有第一焊盘和第二焊盘的半导体衬底中形成存储节点接触来形成半导体器件的接触的方法。 存储节点触点连接到第二焊盘。 与存储节点接触的位线通过间隔物电绝缘并电连接到第一焊盘。

公开(公告)号：US20130011989A1

公开(公告)日：2013-01-10

申请号：US13540996

申请日：2012-07-03

申请人： Jong-Chul Park ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Sang-Sup Jeong

IPC分类号： H01L21/8242

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10876

摘要： In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.

摘要翻译： 在制造DRAM器件的方法中，在衬底中形成掩埋型栅极。 掩埋型栅极上形成封盖绝缘层图案。 形成填充封盖绝缘层图案的部分之间的间隙的导电层图案，以及覆盖导电层图案和封盖绝缘层图案的绝缘夹层。 蚀刻绝缘中间层，导电层图案，封盖绝缘层图案和基板的上部以形成开口，以及与第一焊盘区域接触的第一焊盘电极。 间隔件形成在对应于第二垫区域的开口的侧壁上。 第二焊盘电极形成在开口中。 形成与第二焊盘电极电连接的位线和与第一焊盘电极电连接的电容器。

公开(公告)号：US07572711B2

公开(公告)日：2009-08-11

申请号：US11173189

申请日：2005-06-30

申请人： Jong-Chul Park ,  Sang-Sup Jeong

发明人： Jong-Chul Park ,  Sang-Sup Jeong

IPC分类号： H01L21/48

CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894

摘要： In an embodiment, a simplified method of manufacturing a semiconductor device reduces a step between cell and peripheral areas. First and second openings are formed through a plurality of thin layers including a support layer on a substrate. A storage electrode and a guide ring are formed on sidewalls and bottoms of the first and second openings, respectively. A support pattern is formed so that the support layer in the cell area is partially etched and the support layer in the peripheral area remains un-etched, thus the support pattern supports and surrounds the storage electrodes adjacent to each other in the cell area and prevents an etching of a layer underlying the support layer in the peripheral area. A dielectric layer and a plate electrode are formed on the storage electrode to complete a semiconductor device with the reduced step.

摘要翻译： 在一个实施例中，制造半导体器件的简化方法减少了单元和外围区域之间的步骤。 第一和第二开口通过包括基板上的支撑层的多个薄层形成。 存储电极和引导环分别形成在第一和第二开口的侧壁和底部上。 形成支撑图案，使得单元区域中的支撑层被部分蚀刻，并且周边区域中的支撑层保持未蚀刻，因此支撑图案支撑并围绕细胞区域中彼此相邻的存储电极并且防止 蚀刻周边区域中的支撑层下面的层。 在存储电极上形成电介质层和平板电极，以完成具有减小的步骤的半导体器件。

公开(公告)号：US07438765B2

公开(公告)日：2008-10-21

申请号：US11119490

申请日：2005-04-29

申请人： Jong-Chul Park ,  Sang-sup Jeong

发明人： Jong-Chul Park ,  Sang-sup Jeong

IPC分类号： B05B5/025 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： H01J37/32623 ,  H01J2237/334 ,  H01L21/02087 ,  H01L21/67069

摘要： An apparatus for adjusting an etching area of a semiconductor wafer includes an adjustable shielding plate. The adjustable shielding plate includes a plurality of shielding members. Each of the plurality of shielding members are movable between a first position configured to shield a portion of a semiconductor wafer from an etching gas and a second position configured to expose an unshielded etching portion of the semiconductor wafer to the etching gas.

摘要翻译： 用于调整半导体晶片的蚀刻区域的装置包括可调节屏蔽板。 可调节屏蔽板包括多个屏蔽构件。 多个屏蔽部件中的每一个可以在构造成从蚀刻气体屏蔽半导体晶片的一部分的第一位置和被配置为将半导体晶片的非屏蔽蚀刻部分暴露于蚀刻气体的第二位置之间移动。

公开(公告)号：US07109080B2

公开(公告)日：2006-09-19

申请号：US11033447

申请日：2005-01-12

申请人： Yong-Woo Lee ,  Jong-Chul Park ,  O-Ik Kwon ,  Sang-Sup Jeong

发明人： Yong-Woo Lee ,  Jong-Chul Park ,  O-Ik Kwon ,  Sang-Sup Jeong

IPC分类号： H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

摘要翻译： 一种通过在其上形成有第一焊盘和第二焊盘的半导体衬底中形成存储节点接触来形成半导体器件的接触的方法。 存储节点触点连接到第二焊盘。 与存储节点接触的位线通过间隔物电绝缘并电连接到第一焊盘。