公开(公告)号：US20060033152A1

公开(公告)日：2006-02-16

申请号：US11183614

申请日：2005-07-18

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

公开(公告)号：US07473961B2

公开(公告)日：2009-01-06

申请号：US11183614

申请日：2005-07-18

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

摘要翻译： 提供了具有改善的电特性的非易失性存储器件以及制造该非易失性存储器件的方法。 非易失性存储器件包括形成在其上形成有源极和漏极区域的半导体衬底上的栅电极，该栅极电极介于半导体衬底和栅电极之间，并且包括电子隧穿层和 电荷捕获层和插入在栅电极和电荷捕获层之间的电子反向穿隧防止层防止栅电极中的电子通过电荷捕获层反向隧穿，并且由具有 工作功能比栅电极高。

公开(公告)号：US20060027854A1

公开(公告)日：2006-02-09

申请号：US11200491

申请日：2005-08-09

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.

公开(公告)号：US07586137B2

公开(公告)日：2009-09-08

申请号：US11200491

申请日：2005-08-09

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.

摘要翻译： 提供了具有非对称沟道结构的非易失性存储器件。 非易失性存储器件包括形成在半导体衬底中并掺杂有n型杂质的半导体衬底，源极区和漏极区，包括隧穿层的俘获结构，其被布置在 半导体衬底和通过其电荷载流子被隧道化;以及电荷俘获层，其形成在隧穿层上并俘获隧穿电荷载流子;形成在俘获结构和暴露的半导体衬底上的栅极绝缘层，栅极 形成在栅极绝缘层上的电极和形成在源极区域和漏极区域之间的沟道区域，并且包括形成在捕获结构的下部的第一沟道区域和形成在栅极绝缘层的下部的第二沟道区域 所述第一沟道区的阈值电压低于所述第二沟道区的阈值电压。

公开(公告)号：US07700437B2

公开(公告)日：2010-04-20

申请号：US12183553

申请日：2008-07-31

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/8247

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US07420243B2

公开(公告)日：2008-09-02

申请号：US11248691

申请日：2005-10-12

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US20080286927A1

公开(公告)日：2008-11-20

申请号：US12183553

申请日：2008-07-31

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US20060141708A1

公开(公告)日：2006-06-29

申请号：US11248691

申请日：2005-10-12

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US20060091458A1

公开(公告)日：2006-05-04

申请号：US11265720

申请日：2005-11-02

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Byou-ree Lim

IPC分类号： H01L29/94

CPC分类号： H01L29/66833 ,  H01L29/40117 ,  H01L29/7923

摘要： Provided are a nonvolatile memory device that has enhanced endurance and can accurately read stored data, and a method of manufacturing the same. The nonvolatile memory device includes a trench formed in a semiconductor substrate, a gate electrode formed in the trench, a gate electrode insulating layer interposed between the gate electrode and bottom and lower sidewalls of the trench, a trap structure interposed between upper sidewalls of the trench and the gate electrode and comprising a tunneling layer, a trapping layer, and a blocking layer, and source and drain regions formed on both sides of the semiconductor substrate with respect to the trench, in which the gate electrode insulating layer is not formed and partially overlapped by the trapping layer.

摘要翻译： 提供了具有增强的耐久性并且可以准确地读取存储的数据的非易失性存储器件及其制造方法。 非易失性存储器件包括形成在半导体衬底中的沟槽，形成在沟槽中的栅电极，介于沟槽的栅电极和底侧与下侧壁之间的栅电极绝缘层，夹在沟槽的上侧壁之间的陷阱结构 和栅电极，其包括隧道层，捕获层和阻挡层，以及形成在半导体衬底的相对于沟槽的两侧的源极和漏极区域，其中不形成栅电极绝缘层并且部分地 由捕获层重叠。

公开(公告)号：US07394127B2

公开(公告)日：2008-07-01

申请号：US11047764

申请日：2005-02-02

申请人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

发明人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

摘要翻译： 非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。 电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。 栅电极设置在电荷存储氧化物层上。 至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。 通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作， 漏区，其中形成有卤素离子注入区。