公开(公告)号：US20050184334A1

公开(公告)日：2005-08-25

申请号：US11047764

申请日：2005-02-02

申请人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

发明人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/792

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

摘要翻译： 非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。 电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。 栅电极设置在电荷存储氧化物层上。 至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。 通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作， 漏区，其中形成有卤素离子注入区。

公开(公告)号：US07394127B2

公开(公告)日：2008-07-01

申请号：US11047764

申请日：2005-02-02

申请人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

发明人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

摘要翻译： 非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。 电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。 栅电极设置在电荷存储氧化物层上。 至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。 通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作， 漏区，其中形成有卤素离子注入区。

公开(公告)号：US07184316B2

公开(公告)日：2007-02-27

申请号：US11038726

申请日：2005-01-19

申请人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

发明人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

摘要翻译： 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 将第二电压施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

公开(公告)号：US20050162925A1

公开(公告)日：2005-07-28

申请号：US11038726

申请日：2005-01-19

申请人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

发明人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

摘要翻译： 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 第二电压被施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

公开(公告)号：US20070117300A1

公开(公告)日：2007-05-24

申请号：US11623384

申请日：2007-01-16

申请人： Jung-Il Lee ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sang-Su Kim

发明人： Jung-Il Lee ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sang-Su Kim

IPC分类号： H01L21/8238 ,  H01L27/12

CPC分类号： H01L21/76259 ,  H01L21/76254

摘要： A silicon-on-insulator (SOI) semiconductor substrate includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrates an SOI layer formed on the buried oxide layer, and a diffusion barrier layer interposed between the buried oxide layer and the SOI layer, wherein the diffusion barrier layer is an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer.

摘要翻译： 绝缘体上硅（SOI）半导体衬底包括半导体衬底，在半导体衬底上形成的掩埋氧化物层，形成在掩埋氧化物层上的SOI层，以及介于掩埋氧化物层和SOI层之间的扩散阻挡层 其中所述扩散阻挡层是与所述掩埋氧化物层相比具有较低杂质扩散系数的绝缘层。

公开(公告)号：US20060208303A1

公开(公告)日：2006-09-21

申请号：US11378505

申请日：2006-03-17

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US07170794B2

公开(公告)日：2007-01-30

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US07045850B2

公开(公告)日：2006-05-16

申请号：US10844783

申请日：2004-05-13

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 依次形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层构成的三层，然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20050088879A1

公开(公告)日：2005-04-28

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US07183172B2

公开(公告)日：2007-02-27

申请号：US10397447

申请日：2003-03-26

申请人： Jung-Il Lee ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sang-Su Kim

发明人： Jung-Il Lee ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sang-Su Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76259 ,  H01L21/76254

摘要： A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

摘要翻译： 提供了一种形成SOI半导体衬底的方法和由此形成的SOI半导体衬底。 该方法包括在半导体衬底上顺序地形成掩埋氧化物，扩散阻挡层和SOI层。 与掩埋氧化物层相比，扩散阻挡层由具有较低杂质扩散系数的绝缘层形成。 扩散阻挡层用于防止注入到SOI层中的杂质扩散到掩埋氧化物层或半导体衬底中。