公开(公告)号：US07932154B2

公开(公告)日：2011-04-26

申请号：US12007097

申请日：2008-01-07

申请人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

发明人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

IPC分类号： H01L21/334

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

摘要翻译： 在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案， 电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极 在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及 覆盖屏蔽层图案的栅电极和栅极绝缘层。

公开(公告)号：US07361560B2

公开(公告)日：2008-04-22

申请号：US11033156

申请日：2005-01-12

申请人： Jai-Dong Lee ,  Ki-Chul Kim ,  In-Wook Cho

发明人： Jai-Dong Lee ,  Ki-Chul Kim ,  In-Wook Cho

IPC分类号： H01L21/336

CPC分类号： H01L21/022 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/3144 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charges, nitrogenizing surface of the second dielectric layer, and forming a third dielectric layer the nitridedsecond dielectric layer.

摘要翻译： 提供一种用于制造用于非易失性存储单元的电介质层结构的方法。 一种方法包括形成用于在半导体衬底上隧穿的第一电介质层，在第一电介质层上形成第二电介质层以存储电荷，使第二电介质层的氮化表面，以及形成第三介电层氮化二次介电层。

公开(公告)号：US07345925B2

公开(公告)日：2008-03-18

申请号：US11426387

申请日：2006-06-26

申请人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

发明人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/14

摘要： Erasure methods for a nonvolatile memory cell that includes a gate electrode on a substrate, source and drain regions in the substrate at respective sides of the gate electrode, and a charge storage layer interposed between the gate electrode and the substrate. A nonzero first voltage is applied to the source region starting at a first time. While continuing to apply the first nonzero voltage to the source region, a second voltage having an opposite polarity to the first voltage is applied to the gate electrode starting at a second time later than the first time. The second voltage may increase in magnitude, e.g., stepwise, linearly and/or along a curve, after the second time.

摘要翻译： 一种非易失性存储单元的擦除方法，包括基板上的栅极电极，栅电极各侧的基板中的源极和漏极区域以及介于栅电极和基板之间的电荷存储层。 从第一次开始，向源区域施加非零的第一电压。 在继续向源极区域施加第一非零电压的同时，比第一时间晚的第二时间将栅极电极施加具有与第一电压相反的极性的第二电压。 在第二次之后，第二电压的幅度可以例如逐步地，线性地和/或沿曲线增加。

公开(公告)号：US20070036003A1

公开(公告)日：2007-02-15

申请号：US11426387

申请日：2006-06-26

申请人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

发明人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/14

摘要： Erasure methods are provided for a nonvolatile memory cell that includes a gate electrode on a substrate, source and drain regions in the substrate at respective sides of the gate electrode, and a charge storage layer interposed between the gate electrode and the substrate. A nonzero first voltage is applied to the source region starting at a first time. While continuing to apply the first nonzero voltage to the source region, a second voltage having an opposite polarity to the first voltage is applied to the gate electrode starting at a second time later than the first time. The second voltage may increase in magnitude, e.g., stepwise, linearly and/or along a curve, after the second time.

摘要翻译： 提供了一种非易失性存储单元的擦除方法，该非易失性存储单元包括衬底上的栅电极，栅电极各侧的衬底中的源区和漏区以及置于栅电极和衬底之间的电荷存储层。 从第一次开始，向源区域施加非零的第一电压。 在继续向源极区域施加第一非零电压的同时，比第一时间晚的第二时间将栅极电极施加具有与第一电压相反的极性的第二电压。 在第二次之后，第二电压的幅度可以例如逐步地，线性地和/或沿曲线增加。

公开(公告)号：US07129591B2

公开(公告)日：2006-10-31

申请号：US10982685

申请日：2004-11-04

申请人： Sang-Su Kim ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

发明人： Sang-Su Kim ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

摘要翻译： 公开了具有对准键的半导体器件及其制造方法。 半导体器件包括具有单元区域和对准键区域的半导体衬底。 限定电池有源区的隔离层设置在半导体衬底的单元区域中。 电池电荷存储层图案跨越电池有源区域设置。 对准电荷存储层图案设置在半导体衬底的对准键区域中。 在对准电荷存储层图案中自对准的对准沟槽形成在半导体衬底的对准键区域中。

公开(公告)号：US20060091458A1

公开(公告)日：2006-05-04

申请号：US11265720

申请日：2005-11-02

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Byou-ree Lim

IPC分类号： H01L29/94

CPC分类号： H01L29/66833 ,  H01L29/40117 ,  H01L29/7923

摘要： Provided are a nonvolatile memory device that has enhanced endurance and can accurately read stored data, and a method of manufacturing the same. The nonvolatile memory device includes a trench formed in a semiconductor substrate, a gate electrode formed in the trench, a gate electrode insulating layer interposed between the gate electrode and bottom and lower sidewalls of the trench, a trap structure interposed between upper sidewalls of the trench and the gate electrode and comprising a tunneling layer, a trapping layer, and a blocking layer, and source and drain regions formed on both sides of the semiconductor substrate with respect to the trench, in which the gate electrode insulating layer is not formed and partially overlapped by the trapping layer.

摘要翻译： 提供了具有增强的耐久性并且可以准确地读取存储的数据的非易失性存储器件及其制造方法。 非易失性存储器件包括形成在半导体衬底中的沟槽，形成在沟槽中的栅电极，介于沟槽的栅电极和底侧与下侧壁之间的栅电极绝缘层，夹在沟槽的上侧壁之间的陷阱结构 和栅电极，其包括隧道层，捕获层和阻挡层，以及形成在半导体衬底的相对于沟槽的两侧的源极和漏极区域，其中不形成栅电极绝缘层并且部分地 由捕获层重叠。

公开(公告)号：US07586137B2

公开(公告)日：2009-09-08

申请号：US11200491

申请日：2005-08-09

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.

摘要翻译： 提供了具有非对称沟道结构的非易失性存储器件。 非易失性存储器件包括形成在半导体衬底中并掺杂有n型杂质的半导体衬底，源极区和漏极区，包括隧穿层的俘获结构，其被布置在 半导体衬底和通过其电荷载流子被隧道化;以及电荷俘获层，其形成在隧穿层上并俘获隧穿电荷载流子;形成在俘获结构和暴露的半导体衬底上的栅极绝缘层，栅极 形成在栅极绝缘层上的电极和形成在源极区域和漏极区域之间的沟道区域，并且包括形成在捕获结构的下部的第一沟道区域和形成在栅极绝缘层的下部的第二沟道区域 所述第一沟道区的阈值电压低于所述第二沟道区的阈值电压。

公开(公告)号：US20080286927A1

公开(公告)日：2008-11-20

申请号：US12183553

申请日：2008-07-31

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US20060157775A1

公开(公告)日：2006-07-20

申请号：US11378295

申请日：2006-03-20

申请人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

发明人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

公开(公告)号：US20060141708A1

公开(公告)日：2006-06-29

申请号：US11248691

申请日：2005-10-12

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。