公开(公告)号：US06313670B1

公开(公告)日：2001-11-06

申请号：US09433099

申请日：1999-11-03

申请人： Ki-whan Song ,  Chan-jong Park

发明人： Ki-whan Song ,  Chan-jong Park

IPC分类号： H03K300

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current control circuit capable of minimizing changes in an output high voltage VOH and an output low voltage VOL and quickly and accurately bringing a divided voltage to a steady state, and a packet-type semiconductor memory device including the current control circuit. The current control circuit includes a first differential amplification type buffer for transmitting the voltage of a first pad, that is, the output high voltage VOH, without change in response to a current control enable signal, a second differential amplification type buffer for transmitting the voltage of a second pad, that is, the output low voltage VOL, without change in response to the current control enable signal, and a voltage divider for dividing a voltage ranging between the voltage outputs of the first and second differential amplification buffers, and outputting the divided voltage. Accordingly, in the packet-type semiconductor memory device including the current control circuit, the current control circuit minimizes changes in the output high voltage VOH and the output low voltage VOL and quickly and accurately brings a divided voltage to a steady state, so that the current driving capability of an output driver for driving the second pad can be quickly controlled.

摘要翻译： 一种电流控制电路，其能够使输出高电压VOH和输出低电压VOL的变化最小化，并将分压后的电压快速准确地设定为稳定状态，以及包括电流控制电路的分组型半导体存储器件。 电流控制电路包括：第一差分放大型缓冲器，用于传输第一焊盘的电压，即输出高电压VOH，而不改变响应于电流控制使能信号;第二差分放大型缓冲器，用于传输电压 的第二焊盘，即输出低电压VOL，而不响应于电流控制使能信号而变化;以及分压器，用于分压第一和第二差分放大缓冲器的电压输出之间的电压范围，并输出 分压。 因此，在包括电流控制电路的分组型半导体存储器件中，电流控制电路使输出高电压VOH和输出低电压VOL的变化最小化，并且将分压后的电压快速准确地导入稳定状态， 可以快速地控制用于驱动第二焊盘的输出驱动器的电流驱动能力。

公开(公告)号：US07567452B2

公开(公告)日：2009-07-28

申请号：US11637519

申请日：2006-12-12

申请人： Ki-whan Song ,  Yeong-taek Lee

发明人： Ki-whan Song ,  Yeong-taek Lee

IPC分类号： G11C11/02

CPC分类号： G11C11/24

摘要： A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the word lines and each of the bit lines and stores at least two bits of data; and a plurality of sense amplifiers, each of which amplifies a voltage difference between the bit lines, the bit lines being located at opposite sides of each of the plurality of sense amplifiers.

摘要翻译： 公开了一种具有开放位线结构的多级动态存储器件。 多级动态存储装置包括多个字线; 设置在开放位线结构中的多个位线; 多个存储单元，每个存储单元连接到每个字线和每个位线，并存储至少两位数据; 以及多个读出放大器，每个读出放大器放大位线之间的电压差，位线位于多个读出放大器的每一个的相对侧。

公开(公告)号：US07906397B2

公开(公告)日：2011-03-15

申请号：US12410010

申请日：2009-03-24

申请人： Ki-whan Song ,  Byung-Gook Park

发明人： Ki-whan Song ,  Byung-Gook Park

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.

摘要翻译： 非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对 在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。 制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个 并且形成连接柱子并跨越字线上方的位线。

公开(公告)号：US07505302B2

公开(公告)日：2009-03-17

申请号：US11638002

申请日：2006-12-13

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： G11C11/24 ,  G11C5/06 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/565 ,  G11C7/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2207/002

摘要： A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.

摘要翻译： 多级动态存储器件包括被分成主位线对和子位线对的位线对，连接在主位线对之间和子位线之间的第一和第二读出放大器 分别在主位对和子位对之间交叉耦合的对，第一和第二耦合电容器; 以及分别与第一和第二耦合电容器并联连接并且其电容由控制电压信号调节的第一和第二校正电容器。

公开(公告)号：US20070161181A1

公开(公告)日：2007-07-12

申请号：US11649478

申请日：2007-01-04

申请人： Ki-whan Song ,  Hoon Jeong

发明人： Ki-whan Song ,  Hoon Jeong

IPC分类号： H01L21/8242

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/4236 ,  H01L29/7841

摘要： Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other can be increased, while an area of a junction region where the channel body contact source and drain regions can be reduced. As a result, capacitance of the channel body can be increased, and a generation of leakage current through the second junction region can be reduced. The application of a back bias to the cylindrical auxiliary gates can improve a charge storage capability of the channel body.

摘要翻译： 提供了一种无电容器DRAM（动态随机存取存储器）及其制造方法。 在无电容器DRAM中，在体衬底内形成一对圆柱形辅助栅极。 因此，可以增加在圆柱形辅助栅极彼此接触的区域处形成的通道体积的体积，同时可以减小沟道体接触源极和漏极区域的接合区域的面积。 结果，可以增加通道体的电容，并且可以减少通过第二结区的漏电流的产生。 向圆柱形辅助门施加反向偏压可以改善通道体的电荷存储能力。

公开(公告)号：US08575672B2

公开(公告)日：2013-11-05

申请号：US13047403

申请日：2011-03-14

申请人： Ki-whan Song ,  Byung-Gook Park

发明人： Ki-whan Song ,  Byung-Gook Park

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.

公开(公告)号：US07633117B2

公开(公告)日：2009-12-15

申请号：US11649478

申请日：2007-01-04

申请人： Ki-whan Song ,  Hoon Jeong

发明人： Ki-whan Song ,  Hoon Jeong

IPC分类号： H01L29/792

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/4236 ,  H01L29/7841

摘要： Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other can be increased, while an area of a junction region where the channel body contact source and drain regions can be reduced. As a result, capacitance of the channel body can be increased, and a generation of leakage current through the second junction region can be reduced. The application of a back bias to the cylindrical auxiliary gates can improve a charge storage capability of the channel body.

摘要翻译： 提供了一种无电容器DRAM（动态随机存取存储器）及其制造方法。 在无电容器DRAM中，在体衬底内形成一对圆柱形辅助栅极。 因此，可以增加在圆柱形辅助栅极彼此接触的区域处形成的通道体积的体积，同时可以减小沟道体接触源极和漏极区域的接合区域的面积。 结果，可以增加通道体的电容，并且可以减少通过第二结区的漏电流的产生。 向圆柱形辅助门施加反向偏压可以改善通道体的电荷存储能力。

公开(公告)号：US20070166933A1

公开(公告)日：2007-07-19

申请号：US11622584

申请日：2007-01-12

申请人： Ki-whan Song ,  Chang-kyun Kim

发明人： Ki-whan Song ,  Chang-kyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/66772 ,  H01L29/7841

摘要： Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.

摘要翻译： 形成无电容器的DRAM单元的方法包括通过形成具有从其延伸的沟道区突起并且通过电隔离区围绕沟道区突起的第一半导体晶片来形成场效应晶体管。 然后去除第一半导体晶片的背面的一部分以限定具有与沟道区域突起和电隔离区域相对延伸的主表面的半导体层。 在主表面上形成栅电极。 栅电极与沟道区突起相对延伸。 源极和漏极区域形成在栅电极的相对侧上的半导体层中。

公开(公告)号：US20070139994A1

公开(公告)日：2007-06-21

申请号：US11637519

申请日：2006-12-12

申请人： Ki-whan Song ,  Yeong-taek Lee

发明人： Ki-whan Song ,  Yeong-taek Lee

IPC分类号： G11C11/24

CPC分类号： G11C11/24

摘要： A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the word lines and each of the bit lines and stores at least two bits of data; and a plurality of sense amplifiers, each of which amplifies a voltage difference between the bit lines, the bit lines being located at opposite sides of each of the plurality of sense amplifiers.

摘要翻译： 公开了一种具有开放位线结构的多级动态存储器件。 多级动态存储装置包括多个字线; 设置在开放位线结构中的多个位线; 多个存储单元，每个存储单元连接到每个字线和每个位线，并存储至少两位数据; 以及多个读出放大器，每个读出放大器放大位线之间的电压差，位线位于多个读出放大器的每一个的相对侧。

公开(公告)号：US06366113B1

公开(公告)日：2002-04-02

申请号：US09716557

申请日：2000-11-20

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： H03K30233

CPC分类号： H03K3/013 ,  H03K3/012 ,  H03K3/356139

摘要： A data receiver is provided for stabilizing a reference voltage to which input data is compared. The data receiver includes a differential amplification flip flop for comparing input data to a reference voltage in response to a clock signal, an amplifier for amplifying the results of the comparison, a latch for storing the logic level of the input data, and a counter coupling circuit for reducing the variation of the reference voltage caused by the operation of the differential amplification flip flop in response to an inverted clock signal. In the data receiver, the reference voltage is stably preserved without minimized variation. Also, there is substantially no consumption of direct current (DC) when the data receiver operates.

摘要翻译： 提供数据接收器用于稳定比较输入数据的参考电压。 数据接收机包括差分放大触发器，用于响应于时钟信号将输入数据与参考电压进行比较，用于放大比较结果的放大器，用于存储输入数据的逻辑电平的锁存器和反耦合器 电路，用于响应于反相时钟信号减小由差分放大触发器的操作引起的参考电压的变化。 在数据接收机中，参考电压被稳定地保持而没有最小化的变化。 此外，当数据接收器工作时，基本上不消耗直流电（DC）。