公开(公告)号：US20230042619A1

公开(公告)日：2023-02-09

申请号：US17974740

申请日：2022-10-27

Applicant: Kioxia Corporation

Inventor： Hirokuni YANO ,  Shinichi KANNO ,  Toshikatsu HIDA ,  Hidenori MATSUZAKI ,  Kazuya KITSUNAI ,  Shigehiro ASANO

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

公开(公告)号：US20240111416A1

公开(公告)日：2024-04-04

申请号：US18532267

申请日：2023-12-07

Applicant: Kioxia Corporation

Inventor： Kazuya KITSUNAI ,  Shinichi KANNO ,  Hirokuni YANO ,  Toshikatsu HIDA ,  Junji YANO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

公开(公告)号：US20210294526A1

公开(公告)日：2021-09-23

申请号：US16996984

申请日：2020-08-19

Applicant: Kioxia Corporation

Inventor： Ryuji NISHIKUBO ,  Hirokuni YANO

IPC: G06F3/06 ,  G06F7/58

Abstract: A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.