公开(公告)号：US20230042619A1

公开(公告)日：2023-02-09

申请号：US17974740

申请日：2022-10-27

Applicant: Kioxia Corporation

Inventor： Hirokuni YANO ,  Shinichi KANNO ,  Toshikatsu HIDA ,  Hidenori MATSUZAKI ,  Kazuya KITSUNAI ,  Shigehiro ASANO

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

公开(公告)号：US20240111416A1

公开(公告)日：2024-04-04

申请号：US18532267

申请日：2023-12-07

Applicant: Kioxia Corporation

Inventor： Kazuya KITSUNAI ,  Shinichi KANNO ,  Hirokuni YANO ,  Toshikatsu HIDA ,  Junji YANO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

公开(公告)号：US20220066684A1

公开(公告)日：2022-03-03

申请号：US17147519

申请日：2021-01-13

Applicant: Kioxia Corporation

Inventor： Chihoko SHIGETA ,  Kazuya KITSUNAI

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a first and second nonvolatile memory each including a plurality of memory cells; and a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory. The memory controller is configured to change a setting of at least one unperformed write process among the first set and second set of write processes based on differences in progress between the first set and second set of write processes, the first set and second set of write processes being performed in parallel.

公开(公告)号：US20230185469A1

公开(公告)日：2023-06-15

申请号：US17839301

申请日：2022-06-13

Applicant: Kioxia Corporation

Inventor： Kazuya KITSUNAI

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/061 ,  G06F3/0652 ,  G06F3/0679

Abstract: According to one embodiment, a controller manages a first block set being a set of blocks in which a remaining time is a first time and a second block set being a set of blocks in which a remaining time is a second time. The controller calculates a first rewrite speed based on the first time and a number of blocks included in the first block set. The controller calculates a second rewriting speed based on the second time and a sum of the number of blocks included in the first block set and the number of blocks included in the second block set. The controller determines a maximum rewriting speed among the first rewrite speed and the second rewriting speed. The controller performs the rewrite operation at the determined maximum rewrite speed.

公开(公告)号：US20210073118A1

公开(公告)日：2021-03-11

申请号：US16787133

申请日：2020-02-11

Applicant: Kioxia Corporation

Inventor： Yoko MASUO ,  Yosuke MITSUMASU ,  Kazuya KITSUNAI

IPC: G06F12/02 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.